Parameter Extraction of MOSFETs Operated at Low Temperature

Abstract

Abstract. In this paper, an overview is given of the methods for practical parameter extraction for MOSFETs operated at cryogenic temperatures. The methods considered are based on the input characteristics of the device, from which the charge threshold voltage, the subthreshold slope, the effective mobility, the series resistance and the effective gate length is derived. Whenever possible, the physical basis of the mostly semi-empirical methods will be outlined. Finally, pitfalls and problems, related to low temperature MOSFET characterisation, like transient and freeze-out effects, self-heating, etc, are briefly discussed.

Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs

“…From Table 3 and Figure 4, we observed an increase by a factor 2 of the UTB's series resistance SD when decreasing the temperature from 300 K to 77 K. This trend has been also observed for bulk -MOSFETs [24]. Indeed, below 150 K, the freeze-out effect of the doping impurities leads to an increase of the parasitic series resistance as reported in [25].…”

“…[15,17]. On the other side, Simoen et al [24] used a similar analysis and found = 2.08 for 77 K and = 1.92 for = 300 K for MOS devices having a high resistive silicon substrate. The change of value is attributed to a change of the scattering process.…”

“…This is particularly important at low temperature for which the channel resistance is lowered by the enhancement of the mobility. Since SD and eff are both critical parameters for device modeling, many studies were published in the past decades for both room and cryogenics temperatures [24].…”

“…), similar low temperature research and deep analyses started on SOI MOSFETs, when focusing on the operation mode [19,20], threshold voltage [21,22], accentuated self-heating phenomenon [23], and parameters' extraction [24,25].…”

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

“…Furthermore, accounting for the hopping current leads to a SS theory that explains the measured SS roll-off from room down to sub-Kelvin temperature [81]. Besides the saturation of the subthreshold slope, oscillations in weak inversion have been measured in the current characteristics of some devices fabricated in advanced and mature CMOS technologies [74], [76], [83]. These oscillations are most prominent at low drain bias (in the order of 1-10 mV) and temperatures lower than ≈ 36 K. Simoen et al hint at a resonant tunneling current to be responsible for this phenomenon [83].…”