Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

Minh, Quan Duong; Drazdziulis, Mindaugas; Larsson-Edefors, Per; Bengtsson, Lars

doi:10.1109/isqed.2006.97

Cited by 20 publications

(9 citation statements)

References 5 publications

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“…To solve (1.3) and (1.6), we can first fix k and find the optimal S(k) so that the power consumption is minimized for the given k. Then, we compare the power consumption for different k to obtain the overall optimal S. to its size M : P m (M ). There is some published work on comprehensive power models of SRAM [12,32,49]. But these detailed "white box" models do not show the direct relationship between the power consumption and the memory D R A F T October 27, 2010, 11:34pm D R A F T size.…”

Section: Problem Formulationmentioning

confidence: 99%

Energy‐Efficient Internet Infrastructure

Jiang

Prasanna

2012

Energy‐Efficient Distributed Computing Systems

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Internet is built as a packet-switching network. The kernel function of Internet infrastructure, including routers and switches, is to forward the packets that are received from one subnet to another subnet. The packet forwarding is accomplished by using the header information extracted from a packet to look up the forwarding table maintained in the routers/ switches. Due to rapid growth of network traffic, packet forwarding has long been a performance bottleneck in routers/ switches.

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Section: Problem Formulationmentioning

confidence: 99%

Energy‐Efficient Internet Infrastructure

Jiang

Prasanna

2012

Energy‐Efficient Distributed Computing Systems

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“…SRAMs bitcells' energy accounts for more than 80% of SRAMs' total energy, while other components such as sense-amplifiers, wordline/bitline drivers, address decoders and writing circuits only occupy less than 20% [24]. Therefore, SRAMs bitcells' energy is the main concern in our analysis.…”

Section: Scale As Well As Standard Cellsmentioning

confidence: 99%

Misleading energy and performance claims in sub/near threshold digital systems

Zhang

Huang

et al. 2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Many of us in the field of ultra-low-V dd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower V dd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different V th definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's V dd and energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need V dd to compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold V dd can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-V dd systems. The outlined pitfalls also shed light on future directions in this field.

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“…These tables can be approximated as 2 KB, 32-bit wide memories. An access to such a memory in 65 nm CMOS at 0.9 V would consume approximately 5.7 pJ [27].…”

Section: Memory Controller Architecturementioning

confidence: 99%

Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory

Choudhury

Ringgenberg

Rixner

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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This paper introduces a class of single-ended coding schemes to reduce off-chip interconnect energy consumption. State-of-the-art codes for processor-memory off-chip interfaces require the transmitter and receiver (memory controller and memory) to collaborate using current and previously transmitted values to encode and decode data. Modern embedded systems, however, cannot afford to use such double-ended codes that require specialized memories to participate in the code. In contrast, a single-ended code enables the memory controller to encode data stored in memory and subsequently decode that data when it is retrieved, allowing the use of commodity memories. In this paper, single-ended codes are presented that assign limited-weight codewords using trace-based mapping techniques. Simulation results show that such codes can reduce the energy consumption of an uncoded off-chip interconnect by up to 42.5%.

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Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

Cited by 20 publications

References 5 publications

Energy‐Efficient Internet Infrastructure

Energy‐Efficient Internet Infrastructure

Misleading energy and performance claims in sub/near threshold digital systems

Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory

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