Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing

Suedomi, Yasuhiro; Tamukoh, Hakaru; Tanaka, Michio; Matsuzaka, Kenji; Matsukawa, Takashi

doi:10.1007/978-3-642-42051-1_3

Cited by 6 publications

(5 citation statements)

References 5 publications

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“…4 was used. Here, hardware parameters cnt_size, omega and alpha were set to 6, 1, and 1, respectively, in all simulations, because basic synchronization phenomena could be observed in the experiment [12], which will be shown in the next subsection. The other parameters were assigned appropriate values based on the structure of the simulated network.…”

Section: Resultsmentioning

confidence: 99%

“…Therefore, a reconfigurable platform capable of emulating various sizes and interconnections of pulse-coupled networks is required. As the first step for constructing a reconfigurable platform, we have proposed a digital circuit design of phase oscillators, constructed a network of two pulse-coupled phase oscillators, and observed basic phenomena [12].…”

Section: Introductionmentioning

confidence: 99%

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Parameterized digital hardware design of pulse-coupled phase oscillator networks

et al. 2015

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Parameterized digital hardware design of pulse-coupled phase oscillator networks

et al. 2015

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“…For implementing the spike-based computation and demonstrate the effectiveness of its features, analog VLSI circuits [11,12,13] and digital circuit using field programmable gate arrays (FPGAs) [14,15] have been proposed. In FPGA implementation side, we established that parameterized design allow us to emulate various sizes and interconnections of PCPO networks [15].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Pulse-Coupled Phase Oscillators working as a Reservoir at the Edge of Chaos

Pramanta

Tamukoh

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In the field of neuroscience, reservoir computing (RC) has been viewed as a model of the neuron computational system. RC is a framework for constructing recurrent neural networks, which is used for modeling the parts of the brain to solve the temporal problem. We construct the network inside the reservoir using the Pulse-Coupled Phase Oscillator (PCPO) with neighbor topology connections on field-programmable-gatearray (FPGA). Winfree model is used for PCPO spiking-based. We investigate the stability of the edge phenomenon using the zero one test (Z1-Test) methodology. We evaluate the proposed model on the time series generation tasks. We have successfully implemented and verified using FPGA that the 3x3 and 10x10 PCPO working as a Reservoir on the network.

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“…10,11 For the analog VLSI, we implemented a region-based coupled Markov random field model using pulse-coupled phase oscillators and applied it to image region segmentation. Measurement results showed that the proposed device achieved high efficiency in terms of performance per power consumption.…”

Section: Introductionmentioning

confidence: 99%

Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links

Pramanta¹,

Matsukawa²,

Tamukoh³

2017

JRNAL

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This study proposes an implementation of pulse-coupled phase oscillators over multiple field-programmable-gate-array (FPGA) communication links. Two FPGAs are connected by a gigabit transceiver and a First-In First-Out interface. To verify the effect of communication delay between FPGAs on oscillator synchronization, we implement four oscillators on the multi-FPGA platform. We have successfully observed synchronization over two FPGAs correctly, despite of a 0.1 μs communication delay. The measurement results show that first spike synchronization requires 12.47 μs with a 3.2 Gbps communication throughput.

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Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing

Cited by 6 publications

References 5 publications

Parameterized digital hardware design of pulse-coupled phase oscillator networks

Parameterized digital hardware design of pulse-coupled phase oscillator networks

FPGA Implementation of Pulse-Coupled Phase Oscillators working as a Reservoir at the Edge of Chaos

Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links

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