Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

Abstract

Reconfigurable Computers (RCs) with hardware (FPGA) co-processors can achieve significant performance improvement compared with traditional microprocessor (μP)-based computers for many scientific applications. The potential amount of speedup depends on the intrinsic parallelism of the target application as well as the characteristics of the target platform. In this work, we use image processing applications as a case study to demonstrate how hardware designs are parameterized by the co-processor architecture, particularly the data I/O, i.e., the local memory of the FPGA device and the interconnect between the FPGA and theμP. The local memory has to be used by applications that access data randomly. A typical case belonging to this category is image registration. On the other hand, an application such as edge detection can directly read data through the interconnect in a sequential fashion. Two different algorithms of image registration, the exhaustive search algorithm and the Discrete Wavelet Transform (DWT)-based search algorithm, are implemented on hardware, i.e., Xilinx Vertex-IIPro 50 on the Cray XD1 reconfigurable computer. The performance improvements of hardware implementations are10×and2×, respectively. Regarding the category of applications that directly access the interconnect, the hardware implementation of Canny edge detection can achieve544×speedup.

SAccO: An implementation platform for scalable FPGA accelerators

“…In general, despite a lot of research in the area of reconfigurable computing [1], there are only a few publications on portable and scalable FPGA designs [14,25,26]. They also suggest implementations with varying degrees of parallelism, but do not present a method for automatically determining the hardware parameters as in our framework.…”

“…[25,26]. Therefore, the user logic has a generic parameter R (replication factor) which causes the instantiation of R parallel PEs with R parallel data stream ports.…”