Parametric circuit representation using inductive Boolean functions

Gupta, Aarti; Fisher, Allan L.

doi:10.1007/3-540-56922-7_3

Cited by 19 publications

(16 citation statements)

References 11 publications

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“…Gupta and Fisher [15] introduce a canonical representation for inductive boolean functions (IBF) which resembles an inductive extension of BDDs covering certain classes of inductively-defined hardware circuits. Verification is carried out by symbolic tautology checking on the IBF representation of the circuits.…”

Section: Related Workmentioning

confidence: 99%

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Fully automatic verification and error detection for parameterized iterative sequential circuits

Margaria

1996

Tools and Algorithms for the Construction and Analysis of Systems

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The paper shows how iterative parametric sequential circuits, which are most relevant in practice, can be verified fully automatically. Key observation is that monadic second-order logic on strings provides an adequate level for hardware specification and implementation. This allows us to apply the corresponding decision procedure and counter-model generator implemented in the Mona verification tool, which, for the first time, yields 'push-button' verification, and error detection and diagnosis for the considered class of circuits. As illustrated by means of various versions of counters, this approach captures hierarchical and mixed mode verification, as well as the treatment of varying connectivity in iterative designs. MotivationA clear trend towards reuse of existing designs is the emergence of parametric designs in standard libraries [13]. While such "families of circuits" have been already popular in the hardware verification community for years, where they are the best examples for induction-based reasoning in the hardware application domain, industrial practice did not feature parametric designs in standard libraries because of lack of consolidated methods for their lull-automatic treatment in the design lifecycle. Thus the pressure towards fully automated methods for the analysis, verification, and fault detection of parametric circuits and their specifications grows with the increasing demand for design reuse. Unfortunately, the standard automata theoretic techniques of the hardware community fail here, because the treatment of automata of unbounded size is required. At this stage, Basin and Klarlund discovered that monadic second-order logic on strings, although 'hopeless' from the complexity point of view, is well-behaved in many practical applications, and, in particular, well-suited for the fully automatic verification of *Fakult~t f'dr Mathematik und Informatik, Universitiit Passau, Innstr. 33, 94032 Passau (D), tel: +49 851 509.3096, fax: +49 851 509.3092, ~iziana@fmi.tmi-paasau.dl

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Section: Related Workmentioning

confidence: 99%

“…5In fact, this circuit belongs to the linear parametric class of [15]. It may be modelled by means of their T,TBF structures, providing an adequate inductive definition scheme is at hand.…”

Section: The Iterative Counter: Describing Variable Connectivitymentioning

confidence: 99%

Fully automatic verification and error detection for parameterized iterative sequential circuits

Margaria

1996

Tools and Algorithms for the Construction and Analysis of Systems

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“…Recently, other groups of researchers, e.g., [8,16], have presented methods that exploit this kind of regularity. In [16], parameterized circuits are not described as such.…”

Section: Introductionmentioning

confidence: 99%

“…until some technical conditions indicate a fixed point. Alternatively [8,9] identify classes of parameterized circuits that can be described by recursive BDD tree structures which, for certain classes, correspond to finite automata. While these techniques are novel and can be very effective, they have their drawbacks.…”

Section: Introductionmentioning

confidence: 99%

Hardware Verification using Monadic Second-Order Logic

Basin¹,

Klarlund²

1995

BRICS

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We show how the second-order monadic theory of strings can be used to specify hardware components and their behavior. This logic admits a decision procedure and counter-model generator based on canonical automata for formulas. We have used a system implementing these concepts to verify, or find errors in, a number of circuits proposed in the literature. The techniques we use make it easier to identify regularity in circuits, including those that are parameterized or have parameterized behavioral specifications. Our proofs are semantic and do not require lemmas or induction as would be needed when employing a conventional theory of strings as a recursive data type.

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“…Parameterized circuits are described using BDDs in [8]. This method relies on formulating inductive steps as finite-state devices and does not provide a single specification language.…”

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confidence: 99%

MONA: Monadic Second-Order Logic in Practice

Henriksen¹,

Jensen²,

Jørgensen³

et al. 1995

BRICS

121

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Abstract. The purpose of this article is to introduce Monadic Secondorder Logic as a practical means of specifying regularity. The logic is a highly succinct alternative to the use of regular expressions. We have built a tool MONA, which acts as a decision procedure and as a translator to finitestate automata. The tool is based on new algorithms for minimizing finitestate automata that use binary decision diagrams (BDDs) to represent transition functions in compressed form. A byproduct of this work is a new bottom-up algorithm to reduce BDDs in linear time without hashing.The potential applications are numerous. We discuss text processing, Boolean circuits, and distributed systems. Our main example is an automatic proof of properties for the "Dining Philosophers with Encyclopedia" example by Kurshan and MacMillan. We establish these properties for the parameterized case without the use of induction.Our results show that, contrary to common beliefs, high computational complexity may be a desired feature of a specification formalism.

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Parametric circuit representation using inductive Boolean functions

Cited by 19 publications

References 11 publications

Fully automatic verification and error detection for parameterized iterative sequential circuits

Fully automatic verification and error detection for parameterized iterative sequential circuits

Hardware Verification using Monadic Second-Order Logic

MONA: Monadic Second-Order Logic in Practice

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