Parasitic capacitance and density optimization modeling fill synthesis for VLSI interconnect

Kiat, Joel Yeo Yee; Nyunt, Khine; Yong, Wong Hin

doi:10.1109/acqed.2012.6320469

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Parasitic capacitance and density optimization modeling fill synthesis for VLSI interconnect

Cited by 2 publications

References 11 publications

Timing-Aware Fill Insertions with Design-Rule and Density Constraints

Timing-Aware Fill Insertions with Design-Rule and Density Constraints

Timing-Aware Fill Insertions With Design-Rule and Density Constraints

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