Parasitic Effects Analysis of Bonding Wires Bonding Parameter of Intelligent Power Modules for Three-Phase Motor Control Applications

Abstract

Parasitic parameter analysis is the focus of intelligent power module switch performance research. This paper will utilize the model of 600V/30A intelligent power module and extract the part of circuit layout bonding wires parasitic parameter by Ansys Q3D Extractor, expedition the relationship between physical bonding parameter and parasitic parameter in the intelligent power module circuit. An exact three-phase circuit module of high voltage intelligent power module and bonding wires package module is established. Through Ansys Q3D Extractor, test a series of bonding parameters from the three-phase circuit layout module and extract the parasitic parameters of the bonding wires. The experimental results of the parasitic parameters are analysed and compared, and the influence degree of the bonding parameters on the parasitic parameters is discussed. An improved solution is proposed for the bonding wires of the intelligent power module to reduce the voltage spike that the MOSFET chip during the turn-off process.

Evaluation and Extraction of Equivalent Circuit Parameters for GSG-Type Bonding Wires Using Electromagnetic Simulator

“…When a signal is transmitted through a bonding wire, it becomes a lumped constant line at low frequencies, but at high frequencies, its characteristics cannot be evaluated unless it is analyzed as a distributed constant line and a more rigorous electromagnetic (EM) field problem. Traditionally, the effects of bonding wires have been evaluated using wire inductance per unit length using low frequency approximation [3]- [17]. There are also many documents [18], [19] that investigated the effect of bonding wires using electromagnetic field simulation, but it is different from the connection considering the height of the chip examined in this paper.…”

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

“…Several approaches for close-by integration of GaN power switches together with silicon based CMOS driver and controller logic are on the market or subject of technical evaluations and academic discussions. The package parasitics, namely the package lead inductance, bond wire length related inductances and resistances, as well as the PCB trace inductances are a serious obstacle to the high-speed switching, which is necessary in order to reduce the switching power losses or reduce the size of power converters [1], [2], [3], [4]. While academic research is and has to be done in all fields further industrial development can only occur within commercially promising areas.…”