Pars network: A multistage interconnection network with fault-tolerance capability

Bistouni, Fathollah; Jahanshahi, Mohsen

doi:10.1016/j.jpdc.2014.08.005

Cited by 56 publications

(29 citation statements)

References 40 publications

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“…A large amount of literature has been devoted to provide fault-tolerance in MINs [3]- [23]. The fault-tolerance in these designs are mainly based on using additional hardware.…”

Section: Related Workmentioning

confidence: 99%

“…In [23], fault-tolerance in MINs is provided by increasing the total number of switches in the network, besides of requiring a high number of multiplexers and demultiplexers to connect all processing nodes to the network. On the other hand, this proposal only relies on networks with 2 × 2 switches, being not suitable for networks with switches of higher arity.…”

Section: Related Workmentioning

confidence: 99%

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A Family of Fault-Tolerant Efficient Indirect Topologies

Garzon

Requena

Gómez

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. Indirect topologies are often chosen in the design of HPC systems. Among them, the most commonly used topology is the fat-tree. In this work, we focus on getting the maximum benefits from the network resources by designing a simple indirect topology with very good performance and fault-tolerance properties, while keeping the hardware cost as low as possible. To do that, we propose some extensions to the fat-tree topology to take full advantage of the hardware resources consumed by the topology. In particular, we propose three new topologies with different properties in terms of cost, performance and fault-tolerance. All of them are able to achieve a similar or better performance results than the fat-tree, providing also a good level of fault-tolerance and, contrary to most of the available topologies, these proposals are able to tolerate also faults in the links that connect to end nodes.

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“…A large amount of literature has been devoted to provide fault-tolerance in MINs [3]- [23]. The fault-tolerance in these designs are mainly based on using additional hardware.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A Family of Fault-Tolerant Efficient Indirect Topologies

Garzon

Requena

Gómez

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

View full text Add to dashboard Cite

show abstract

“…Moreover, the parameter that can be used in assessment of the MINs performance in terms of cost, is the cost-effectiveness parameter that in the most reported works [4,27,32,33,35] has been emphasized. Therefore, we will discuss the parameter to a comprehensive review of the hardware costs of the networks.…”

Section: Performance Analysismentioning

confidence: 99%

“…Another component of this system is I/O, where I/O devices are often connected to an I/O bus which is interfaced to memory module of different processors via the interconnection. Therefore, processor, memory hierarchy, and interconnection network are critical components of a parallel system [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

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Scalable crossbar network: a non-blocking interconnection network for large-scale systems

Bistouni

Jahanshahi

2014

J Supercomput

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Interconnection networks (INs) are used in wide applications of multiprocessor systems in order to set up connections between various nodes such as processors and memory modules. However, there is a fundamental problem in INs that has always been considered as one of the most challenging issues in this area. Blocking problem in these networks degrades network performance and consequently the performance of the whole system. In the meantime, the main option for dealing with this problem is the use of non-blocking crossbar networks. However, there are engineering and scaling difficulties when using these networks in large-scale systems. The number of pins on a VLSI chip cannot exceed a few hundreds, which restricts the size of the largest crossbar that should be integrated into a single VLSI chip. Using the idea of multistage implementation of crossbar network can resolve the problem. However, the next problem that arises with this idea is high hardware cost. Therefore, in this paper, a new implementation of crossbar network named scalable crossbar network (SCN) that is a non-blocking network is presented to cope with the aforementioned scaling problems. In addition, performance analysis results show that SCN outperforms multistage crossbar networks and multistage interconnection networks in terms of terminal reliability, mean time to failure, and system failure rate.

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2020

Interconnection Network Reliability Evaluation

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Pars network: A multistage interconnection network with fault-tolerance capability

Cited by 56 publications

References 40 publications

A Family of Fault-Tolerant Efficient Indirect Topologies

A Family of Fault-Tolerant Efficient Indirect Topologies

Scalable crossbar network: a non-blocking interconnection network for large-scale systems

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