Parsim: a parallel trace-driven simulation facility for fast and accurate performance analysis studies

Nguyen, Anh; Wellman, John-David; Bose, Pradip

doi:10.1109/pccc.1997.581530

Cited by 3 publications

(6 citation statements)

References 7 publications

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“…(Application of the fixed, 7000-instruction warmup to cache state was demonstrated to be untrustworthy in Haskins, Jr. and Skadron [2001].) Nguyen et al [1997], on the other hand, approach the problem of warmup analytically as a part of the trace-driven PARSIM parallel microprocessor simulation system. Their formula calculates a function of the cache block width, associativity, the average population density of memory references within the instruction stream, and the average steady-state cache miss ratio.…”

Section: Related Workmentioning

confidence: 99%

“…To accelerate sampled simulation even further, one can avoid FULL-WARMUP by only modeling those interactions that occur within a certain number of instructions prior to each sample cluster [Conte et al 1996;Crowley and Baer 1999;Eeckhout et al 2003;Skadron 2001, 2003;Kessler et al 1991;Nguyen et al 1997]. This approach exploits temporal locality [Hennessy and Patterson 1995]: the propensity of programs to demonstrate a strong correlation between recency of use and next use, for example, of cache blocks.…”

Section: Introductionmentioning

confidence: 99%

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Accelerated warmup for sampled microarchitecture simulation

Haskins

Skadron

2005

ACM Trans. Archit. Code Optim.

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To reduce the cost of cycle-accurate software simulation of microarchitectures, many researchers use statistical sampling: by simulating only a small, representative subset of the end-to-end dynamic instruction stream in cycle-accurate detail, simulation results complete in much less time than simulating the cycle-by-cycle progress of an entire benchmark. In order for sampled simulation results to accurately reflect the nature the full dynamic instruction stream, however, state in the simulated cache and branch predictor must match or closely approximate state as it would have appeared had cycle-accurate simulation been used for the entire simulation. Researchers typically address this issue by prefixing a period of warmup-in which cache and branch predictor state are modeled in addition to programmer-visible architected state-to each cluster of contiguous instructions in the sample.One conservative, but slow approach is to always simulate cache and branch predictor state, whether among the cycle-accurate clusters, or among the instructions preceding each cluster. To save time, warmup heuristics have been proposed, but there is no one-size-fits-all heuristic for any benchmark. More rigorous, analytical warmup approaches are necessary in order to balance the requirements of high accuracy and rapidity from sampled simulations. This paper explores this issue and in particular demonstrates the merits of memory reference reuse latency (MRRL).Relative to the IPC measured by modeling all precluster cache and branch predictor activity, MRRL generated an average error in IPC of less than 1% and simultaneously reduced simulation running times by an average of approximately 50% (or 95% of the maximum potential speedup).

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Accelerated warmup for sampled microarchitecture simulation

Haskins

Skadron

2005

ACM Trans. Archit. Code Optim.

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“…Then Nguyen et al [10] extended this idea to full trace analysis in which intervals overlap each other to form warmup phases. They also devised a heuristic method for their PARSIM to determine the length of a warmup phase using L1 cache hit ratio as the measure to estimate how each simulator node is warmed.…”

Section: Introductionmentioning

confidence: 99%

An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators

Yano

Takasaki

Nakada

et al. 2007

40th Annual Simulation Symposium (ANSS'07)

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This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many intervals. This time-division parallelization is similar to the concept of trace-splitting parallelization but is completely different from this conventional technique because our simulator assures that its result is perfectly equivalent to what a sequential simulator produces. The assurance of the perfect accuracy is endued by a simple failure recovery mechanism; if i-th interval is simulated by a node with an approximate initial machine state which causes invalid result, the interval is simulated again by the node responsible to (i−1)-th interval and thus having the correct state at the beginning of i-th interval. In order to reduce the possibility of the interval failure for efficiency, the fully cycleaccurate simulation for an interval is preceded by a partial and thus fast microarchitectural simulation including that for caches, branch predictors and their interaction in speculative execution. Another important technique is to check the validity of an interval simulation by comparing approximate and correct initial states with respect to their effect to the subsequent execution, rather than the raw values of them. The effectiveness of these techniques are exhibited by our SimpleScalar-based implementation and its evaluation with SPEC CPU95 benchmarks which results that 8-node and 16-node parallel simulations achieve up to 5.8-fold and 9.4-fold speedup respectively.

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“…Nguyen et al [12] on the other hand, approach the problem of warmup analytically as a part of the trace-driven PARSIM parallel microprocessor simulation system. Their formula calculates a function of the cache block width, associativity, the average population density of memory references within the instruction stream, and the average steady-state cache miss ratio.…”

Section: Related Workmentioning

confidence: 99%

“…One method for further accelerating sampled simulations is to avoid fullwarmup by only modeling those interactions that occur within a given number of instructions prior to the cluster [3], [5], [8], [12]. Our technique makes the determination of when to engage cache and branch predictor warmup by exploiting memory reference reuse latencies (MRRL)-a measurement of the number of instructions that elapse between successive references to the same address.…”

Section: Introductionmentioning

confidence: 99%

Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation

Haskins¹,

Skadron

2003 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS 2003.

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Abstract-This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that of the memory references that precede a sample cluster, references that occur nearest to the cluster are more likely to be germane to the execution of the cluster itself. Hence, while modeling all cache and branch predictor interactions that precede a sample cluster would reliably establish their state, this is overkill and leads to longrunning simulations. Instead, accurately establishing simulated cache and branch predictor state can be accomplished quickly by only modeling a subset of the memory references and controlflow instructions immediately preceding a sample cluster.Our technique measures memory reference reuse latencies (MRRLs)-the number of completed instructions between consecutive references to each unique memory location-and uses these data to choose a point prior to each cluster to engage cache hierarchy and branch predictor modeling. By starting cache and branch predictor modeling late in the pre-cluster instruction stream, we were able to reduce overall simulation running times by an average of 90.62% of the maximum potential speedup (accomplished by performing no pre-cluster warmup at all), while generating an average error in IPC of less than 1%, both relative to the IPC generated by warming up all pre-cluster cache and branch predictor interactions.

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Parsim: a parallel trace-driven simulation facility for fast and accurate performance analysis studies

Cited by 3 publications

References 7 publications

Accelerated warmup for sampled microarchitecture simulation

Accelerated warmup for sampled microarchitecture simulation

An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators

Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation

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