Parsing and analysis of a Xilinx FPGA bitstream for generating new hardware by direct bit manipulation in real-time

Roux, Rikus le; Schoor, George van; Vuuren, P.A. Van

doi:10.18489/sacj.v31i1.620

Cited by 3 publications

(6 citation statements)

References 19 publications

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“…The work presented in this paper used the proposed hardware-based reconfiguration method of le Roux et al (2019) to improve the functional density of an application that is typically not reconfigured. These applications in general have strict time constraints and short execution times, which give them excellent functional densities.…”

Section: Resultsmentioning

confidence: 99%

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Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Roux

Schoor

Vuuren

2019

SACJ

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The dynamic reconfiguration of an FPGA has many advantages, but the overhead from the process reduces the functional density of applications. Functional density is an indication of the composite benefits a reconfigured application obtains above its generic counterpart and measures the computational throughput per unit hardware resources. Typically, only quasi-static applications obtain a functional density advantage by dynamically reconfiguring its parameters. Contributing to the functional density reduction of applications with tight time constraints is the overhead to generate a new configuration, and the time it takes to load it onto the device. Normally these applications have to reuse their hardware numerous times between configurations before obtaining a functional density advantage. The most promising reconfiguration method to improve functional density with minimal hardware reuse was one that extracts certain characteristics from the bitstream and then implements a bitstream specialiser that generates new hardware at bit-level while the device is being reconfigured. While it was shown that this method allows reconfiguration of an application in real-time, its effect on functional density was not determined. This paper will show that a significant increase in functional density can be achieved for applications where reconfiguration is required before the next execution cycle of the application.

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Section: Resultsmentioning

confidence: 99%

“…A Xilinx ® Virtex ® -5 XCVFX70T FPGA was used for implementation, since this is the same device le Roux et al (2019) used to showcase their bitstream specialiser. In theory any Xilinx ® FPGA can be used by applying the method proposed by le Roux et al (2019), but the FPGA architectures from other vendors were not analysed.…”

mentioning

confidence: 99%

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Roux

Schoor

Vuuren

2019

SACJ

Self Cite

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“…An FPGA bitstream contains the programming information configuring the programmable logic in the FPGA. Due to the lack of disclosed information about the bitstream format from FPGA vendors, many works have analyzed the format of bitstream [3], [6]- [8]. Ziener et al [3] extracted the content of Look Up Tables (LUTs) in the bitstream of Xilinx Virtex-II and Virtex-II Pro FPGAs to identify intellectual property (IP) cores in the FPGAs.…”

Section: Related Workmentioning

confidence: 99%

“…Ziener et al [3] extracted the content of Look Up Tables (LUTs) in the bitstream of Xilinx Virtex-II and Virtex-II Pro FPGAs to identify intellectual property (IP) cores in the FPGAs. Le Roux et al [6] analyzed the bitstream of Xilinx Virtex-5 FPGAs to manipulate the configuration bits of LUTs for the purpose of reconfiguring the FPGAs in real-time. There are also some related works analyzing the bitstream format of the later Xilinx 7-series FPGAs [7], [8].…”

Section: Related Workmentioning

confidence: 99%

A Deep Learning-Based FPGA Function Block Detection Method With Bitstream to Image Transformation

Chen

Liu

2021

IEEE Access

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In the context of various application scenarios and/or for the sake of strengthening fieldprogrammable gate array (FPGA) security, the system functions of an FPGA design need to be analyzed, which can be achieved by systematically partitioning the FPGA's bitstream into manageable functional blocks and detecting their functionalities thereafter. In this paper, we propose a novel deep learning-based FPGA function block detection method with three major steps. In specific, we first analyze the format of the bitstream to obtain the mapping relationship between the configuration bits and configurable logic blocks because of the discontinuity of the configuration bits in the bitstream for one element. In order to reap the maturity of object detection techniques based on deep learning, our next step is to convert an FPGA bitstream to an image, following the proposed transformation method that takes account of both the adjacency nature of the programmable logic and the high degree of redundancy of configuration information. Once the image is obtained, a deep learning-based object detection algorithm is applied to this transformed image, and the objects detected can be reflected back to determine the function blocks of the original FPGA design. The deep neural network used for function block detection is trained and validated with a specially crafted bitstream/image dataset. Experiments have confirmed high detection accuracy of the proposed function detection method, showing a 98.11% of mean Average Precision (IoU=0.5) for 10 function blocks within a YOLOv3 detector implemented on Xilinx Zynq-7000 SoCs and Zynq UltraScale+ MPSoCs.INDEX TERMS Bitstream-to-image transformation, field-programmable gate array, function block detection.

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“…An FPGA bitstream contains the programming information for an FPGA device, which configures the programmable logic into the FPGA. Because of the lack of disclosed information about the bitstream format from FPGA vendors, many works have analyzed the format of bitstream [1], [33], [34], [35]. Ziener et al [1] extracted the content of LUTs in the bitstream of Xilinx Virtex-II and Virtex-II Pro FPGAs to identify IP cores in the FPGAs.…”

Section: Related Workmentioning

confidence: 99%

A Deep Learning-Based FPGA Function Block Detection Method with Bitstream to Image Transformation

Chen,

Liu

2020

Preprint

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Examining field-programmable gate array (FPGA) bitstream is found to help detect known function blocks, which offers assistance and insight to analyze the circuit's system function. Our goal is to detect one or more than one function block in FPGA design from a complete bitstream by utilizing the latest deep learning techniques, which do not require manually designing features. To this end, in this paper, we propose a deep learning-based FPGA function block detection method by transforming the bitstream into a three-channel color image. In specific, we first analyze the format of the bitstream to find the mapping relationship between the configuration bits and configurable logic blocks. Next, an image-coded representation of bitstream is proposed suitable for deep learning processing. This bitstream-to-image transformation takes into account of the adjacency nature of the programmable logic as well as high degree of redundancy of configuration information. With the color images transformed from bitstreams as the training dataset, a deep learning-based object detection algorithm is applied for generating the function block detection results. The effects of EDA tools, input size of the deep neural network, and the data arrangement of representation on the detection accuracy are explored. The Xilinx Zynq-7000 SoCs and Xilinx Zynq UltraScale+ MPSoCs are adopted to verify the proposed method, and the results show that the mean Average Precision (IoU=0.5) for 10 function blocks is as high as 97.72% for YOLOv3 detector.

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Parsing and analysis of a Xilinx FPGA bitstream for generating new hardware by direct bit manipulation in real-time

Cited by 3 publications

References 19 publications

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

A Deep Learning-Based FPGA Function Block Detection Method With Bitstream to Image Transformation

A Deep Learning-Based FPGA Function Block Detection Method with Bitstream to Image Transformation

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