Partial simulation-driven ATPG for detection and diagnosis of faults in analog circuits

Abstract

In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-undertest, the proposed test generator computes the optimal transient test stimuli in order to detect and isolate a given set of faults. It also computes the optimal set of test nodes to probe at, and the time instants to make measurements. The test generation program accommodates the effects introduced by component tolerances and measurement inaccuracy, and can be tailored to fit the signal generation capabilities of a hardware tester. Experimental results show that the proposed technique can be applied to generate transient tests for both linear and non-linear analog circuits of moderate complexity in reasonably less CPU time. This will significantly impact the test development costs for an analog circuit and will decrease the time-to-market of a product. Finally, the short duration and the easy-to-apply feature of the test stimuli will lead to significant reduction in production test costs.

Automated Selection of Test Frequencies for Fault Diagnosis in Analog Electronic Circuits

“…Here, we follow the harmonic analysis framework which requires that the input stimuli exciting the CUT are sinusoidal signals at different frequencies; solutions based on the wide band stimuli approach (e.g., white noise [10] or arbitrary waveforms [7]) are more efficient in terms of analysis time but provide a reduced signal-to-noise ratio (SNR) and require a more complex test setup.…”

Application-specific low-voltage current amplifier for system-on-chip I/sub DDQ/ test

“…This could result in significant performance degradation and sometimes may even malfunction deviceunder-test (DUT). In a recent study [IO,121 it has been emphasized that the development of high quality built-in current sensors depends on our ability to design an amplifier that meets the following requirements: low area overhead, negligible circuit-under-test performance loss, 0-7803-7596-3/02/$17.00 02002 IEEE reasonable power dissipation, capability of high-frequency measurements, and high sensitivity. In this paper we propose a potential solution that satisfies these requirements.…”

A novel specification based test pattern generation using genetic algorithm and wavelets

“…This paper uses Genetic Algorithm for the generation of the optimal test pattern that detects both catastrophic and parametric faults present in Circuit Under Test (CUT). Previously in many papers genetic algorithm is used for test pattern generation [4], [5]. In their work many node points are considered for detecting the fault in device under test.…”