Partial synthesis through sampling with and without specification

Abstract

In this paper, we present techniques for partial synthesis through sampling mostly for combinational circuits.Here partial synthesis means that most parts of the target circuits are fixed whereas the missing portions must be logic synthesized from scratch. By modeling the missing portions with Look Up Table (LUT) or uninterpreted function (UF), their synthesis and verification problems can be formulated as Quantified Boolean Formulae (QBF). We solve these QBF by repeatedly applying a two step procedure i.e., synthesizing circuits from sample simulation results (necessary conditions) followed by formal verification on the synthesized ones with their specifications for the entire circuits (sufficient conditions). If a circuit is not correct, a counter example is automatically generated which is added to the sampling in the next iteration. With state-of-theart combinational formal equivalence checkers, our experiments show that large circuits having more than hundreds of thousands of gates can be successfully processed with small numbers of repetitions (in the order of hundreds). Next, we extend the techniques in such a way that no formal specifications nor formal verifiers are available, but only simulation models are used for "correct" partial synthesis. This is achieved by searching for multiple different solution circuits for missing portions which behave the same for the sampled inputs but differently with another input. By repeating this process, we can narrow down the search space, and the solution circuit may become only one which should be the "correct" partial synthesis. We show successfully experimental results with small numbers of repetitions for circuits where 32-inputs/32-outputs sub-circuits are missing.

Debugging Methods Through Identification of Appropriate Functions for Internal Gates

“…The techniques shown in [3,4] give a general framework on how to deal with QBF only with SAT solvers. These ideas have also been applied to so called partial logic synthesis in [7].…”

“…Each inserted LUT has the same set of input variables as its original gate. Then, by applying the method in [2,7], we try to find a configuration of the set of LUTs so that the specification and the implementation become logically equivalent.…”

“…Then, another implementation will be created based on the corrected logic function, which may require re-synthesis or synthesis for ECO. Although the method to compute a configuration of LUTs for correction in [2,7] is relatively more efficient than most of the other methods, it can solve up to hundreds of LUTs within a practical runtime. Therefore, it is not practical to replace all of the gates in the given circuit with LUTs, and the number of LUTs inserted into the implementation influence a lot on the runtime.…”

“…Look for a configuration of LUTs for correctionby applying the methods in [2,7] There can be cases where any correction cannot be found for a given implementation with LUTs. There can be varieties of reasons on the failure.…”

“…So, the new gate to be used for replacement may have to realize a complicated logic function with the same inputs and can only be implemented with a set of simple gates, such as, NAND, NOR, etc. As described in the following sections, we utilize an existing method proposed in [2,7] to efficiently generate logic functions for programmable circuits. There are, however, bugs which cannot be corrected if the input variables of the gates remain the same.…”