Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits

Feinstein,; Thornton, Mitchell A.; Miller, '

doi:10.1109/date.2008.4484932

Cited by 15 publications

(12 citation statements)

References 8 publications

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“…Existing approaches (e.g. [12,29,30,31]) provide a good starting point, but mainly focus on reducing quantum cost. Another idea is to adjust the cost function of exact BDD implementations with respect to quantum cost and to synthesize the circuits from the resulting BDDs.…”

Section: Discussionmentioning

confidence: 99%

BDD-based synthesis of reversible logic for large functions

Wille

Drechsler

2009

Proceedings of the 46th Annual Design Automation Conference

269

184

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Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a Binary Decision Diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.

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Section: Discussionmentioning

confidence: 99%

BDD-based synthesis of reversible logic for large functions

Wille

Drechsler

2009

Proceedings of the 46th Annual Design Automation Conference

269

184

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“…Proof: The proof results directly from the canonic property of QMDD of Theorem 1, and following the discussion in [27,28]. □ Let us assume that circuit C of s gates and circuit C' of t gates are two implementations of the same function specification, where t>s. Since Lemma 1 indicates that C and C' are represented by the same QMDD, it is clear that the QMDD size cannot be used as a measure of circuit size complexity.…”

Section: Lemmamentioning

confidence: 99%

On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering

Feinstein¹,

Thornton

2009

2009 39th International Symposium on Multiple-Valued Logic

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“…As a result, reversible logic became an intensely studied research area leading to first approaches for synthesis [8]- [13], optimization [14], [15], verification [16]- [18], testing [19]- [21], and even debugging [22]. But so far only simple circuits have been considered since most of the respective synthesis approaches still rely on Boolean function descriptions like permutations [8], truth tables [9], binary decision diagrams [13], positive-polarity Reed-Muller expansion [10], or Reed-Muller spectra [11].…”

Section: Introductionmentioning

confidence: 99%

SyReC: a programming language for synthesis of reversible circuits

Wille¹,

Offermann²,

Drechsler³

2010

2010 Forum on Specification &Amp; Design Languages (FDL 2010)

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Abstract-Reversible logic serves as a basis for emerging technologies like quantum computing and additionally has applications in low-power design. In particular, since traditional technologies like CMOS are going to reach their limits in the near future, reversible logic has been established as a promising alternative. Thus, in the last years this area started to become intensely studied by researchers. In particular, how to efficiently synthesize complex reversible circuits is an important question. So far, only synthesis approaches are available that rely on Boolean function representations, like e.g. truth tables or decision diagrams.In this paper, we propose the programming language SyReC that allows to specify and afterwards to automatically synthesize reversible circuits. Using an existing programming language for reversible software design as basis, we introduce new concepts, operations, and restrictions allowing the specification of reversible hardware. Furthermore, a hierarchical approach is presented that automatically transforms the respective statements and operations of the new programming language into a reversible circuit. Experiments show that with the proposed method, complex circuits can be easily specified and synthesized while with previous approaches this often is not possible due to the limits caused by truth tables or decision diagrams.

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Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits

Abstract: Abstract

Cited by 15 publications

References 8 publications

BDD-based synthesis of reversible logic for large functions

BDD-based synthesis of reversible logic for large functions

On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering

SyReC: a programming language for synthesis of reversible circuits

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