Partitioning and Placement for Buildable QCA Circuits

Lim, Sung Kyu; Niemier, Mike

doi:10.1007/1-4020-8068-9_10

Cited by 6 publications

(9 citation statements)

References 17 publications

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“…Coplanar crossing is very important for designing QCA circuits; multi-layer QCA has been proposed [4] as an alternative technique to route signals, however it still lacks a physical implementation. At design level, algorithms have been proposed to reduce the number of coplanar wire crossings [9]. In QCA circuits, a reliable operation of coplanar crossing is dependent on the temperature of operation.…”

Section: Introductionmentioning

confidence: 99%

QCA Circuits for Robust Coplanar Crossing

et al. 2007

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In this paper, different circuits of Quantum-dot Cellular Automata (QCA) are proposed for the so-called coplanar crossing. Coplanar crossing is one of the most interesting features of QCA because it allows for mono-layered interconnected circuits, whereas CMOS technology needs different levels of metalization. However, the characteristics of the coplanar crossing make it prone to malfunction due to thermal noise or defects. The proposed circuits exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian plane. This is accomplished using enlarged lines and voting. A Bayesian Network (BN) based simulator is utilized for evaluation; results are provided to assess robustness in the presence of cell defects and thermal effects. The BN simulator provides fast and reliable computation of the signal polarization versus normalized temperature. Simulation of the wire crossing circuits at different operating temperatures is provided with respect to defects and a quantitative metric for performance under temperature variations is proposed and assessed.

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Section: Introductionmentioning

confidence: 99%

QCA Circuits for Robust Coplanar Crossing

et al. 2007

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“…Some of them convert the problem to the direct acyclic graph and aim to resolve this problem. Some researches proposed node duplication, swap node position, back-edge, compose universal logic gate, time division multiplexing in clock-phase, integer linear programming etc., as solutions to reduce or minimise wire crossing [16][17][18][19][20][21]. In this paper, based on the Karnaugh-Map (K-Map), a heuristic method is proposed that reduces the number of wire crossings in the QCA layout.…”

Section: Introductionmentioning

confidence: 99%

Improving logic function synthesis, through wire crossing reduction in quantum‐dot cellular automata layout

Taherifard

2015

IET Circuits, Devices & Systems

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Quantum-dot cellular automata, as the successor of metal-oxide semiconductor field-effect transistors, are one of the promising nanotechnology devices, which have attracted myriad researchers in the recent decade. In this technology, coplanar wire crossing is one of the unique specifications that can reduce its reliability. In the present study, a heuristic method is introduced using the Karnaugh-Map (K-Map) to minimise the number of wire crossing as the first step. Afterwards, it attempts to replace each wire crossing with three non-wire crossing XOR gates that reduce all wire crossings to zero as the second step. Experimental results reveal that, reducing wire crossings to zero, the authors method for 3-variable functions lowers the number of gates about 54, 42, 58 and 59%, respectively, in comparison with K-Map, Genetic, Gate-Optimise and Universal Quantum-dot Cellular Automata Logic Gate (UQCALG) methods. For 4-variable functions, their method decreases the number of gates almost 64 and 58%, respectively.

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“…Also, wire crossing poses a bigger barrier than wire length in QCA architecture [10]. In the classic binary QCAs, wire cross is realized either considering rotated QCA cells in a wire (coplanar wire crossing) or with multilayer crossing.…”

Section: Introductionmentioning

confidence: 99%

Design of Efficient Full Adder in Quantum‐Dot Cellular Automata

Sen

Rajoria

Sikdar

2013

The Scientific World Journal

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Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

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Partitioning and Placement for Buildable QCA Circuits

Cited by 6 publications

References 17 publications

QCA Circuits for Robust Coplanar Crossing

QCA Circuits for Robust Coplanar Crossing

Improving logic function synthesis, through wire crossing reduction in quantum‐dot cellular automata layout

Design of Efficient Full Adder in Quantum‐Dot Cellular Automata

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