Past progress, current status, and future perspective of digital EUV lithography for high-resolution semiconductor manufacturing

Abstract

In this paper, a general review of the past progress, current status and future perspective of MEMS/NEMS based maskless EUV digital lithography for high-resolution semiconductor manufacturing is presented. Starting from the maskless patterning resolution and throughput requirements, we shall discuss the unique characteristics of digital EUV lithography spanning from optical and system-level design, imaging methodology, writing engine, to device process development and fabrication progress achieved. The wafer scan induced image blur impacts maskless writing speed and imaging strategy. The required high demagnification and redundant multiple-pulse exposure help to enable the defect-tolerant printing. Digital EUV lithography allows multiple/sequential stitching exposures in one scanning process without throughput penalty, thus can simplify the patterning process and amplify its competitiveness in high-NA application. Moreover, its grayscale/analog imaging principle not only significantly reduces the data rate but also provides an efficient way to enhance the resolution capability. Dynamics, control and design of electrically damped MEMS/NEMS devices will be examined. A low-temperature LPCVD SiGe process for MEMS/IC integration has been developed and the micromirror fabrication results will be reviewed. It is shown that reflective nanomirrors based maskless approach is one path to cost-effective and defect-tolerant compact EUV lithography, which helps to create emerging opportunities for low-volume but cutting-edge IC applications. Potential processing challenges and scaling issues of nanomirror device technology for a timely insertion of digital EUV lithography into future advanced IC manufacturing will also be discussed.