Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture

Dittmann, Florian; Rettberg, Achim; Weber, Raphael

doi:10.1007/11596356_46

Cited by 2 publications

(2 citation statements)

References 11 publications

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“…In addition, the fully interlocked pipeline allows for extending the architecture to support multiple applications within one implementation. The architecture is described in more detail in [8,9,7,2,3].…”

Section: Mact Architecturementioning

confidence: 99%

Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture

Dittmann

Rettberg

Weber

2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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This paper presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was recently patented and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This paper focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization.

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Section: Mact Architecturementioning

confidence: 99%

Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture

Dittmann

Rettberg

Weber

2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

Self Cite

View full text Add to dashboard Cite

show abstract

Section: Mact Architecturementioning

confidence: 99%

Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture

Giefers

Rettberg

2006

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

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In this paper, we present an approach for low-power driven synthesis based on local frequency/voltage scaling. During the scheduling phase of the High-Level Synthesis (HLS) the design is partitioned into different frequency/voltage islands. Operators within these islands, are encapsulated by wrappers to ensure correct dataflow between the islands. A wrapper consists of a clock generator and input-and output ports. The local clocks are calculated by dividing the global clock signal. With the developed wrappers we are able to automatically integrate local frequency/voltage scaling for our target architecture by our HLS tool. As an example we implement the inverse discrete cosine transformation (IDCT).

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Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture

Cited by 2 publications

References 11 publications

Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture

Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture

Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture

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