Path Selection and Sensor Insertion Flow for Age Monitoring in FPGAs

Ebrahimi, Mohammad; Ghaderi, Zana; Bozorgzadeh, Eli; Navabi, Z.

doi:10.3850/9783981537079_0801

Cited by 10 publications

(6 citation statements)

References 15 publications

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“…With the popularization of built-in self-tests (BISTs) in IC tests, actual on-chip measurements and sensor-based aging monitoring have become the mainstream methods [2,[9][10][11][12][13][14]26,27]. Naouss et al [2] established a low-cost test platform to evaluate FPGA reliability, which supports aging delay measurements for multiple FPGAs at the same time.…”

Section: Aging Tests On Fpgasmentioning

confidence: 99%

“…Refs. [11][12][13][14] employed aging sensors to monitor the delays in critical circuit paths to evaluate FPGA aging. Almost all of these methods can obtain relatively accurate delay data and their measurements are based on RO circuits.…”

Section: Aging Tests On Fpgasmentioning

confidence: 99%

“…Hence, measuring the variations in path delay can quantify the aging degree of a circuit. For a long time, actual on-chip measurements and sensor-based aging monitoring have been the mainstream methods [2,[9][10][11][12][13][14]. Almost all of these methods employ ring oscillator (RO)based circuits to measure path delay.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Huang

Wang

et al. 2022

Sensors

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Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

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Section: Aging Tests On Fpgasmentioning

confidence: 99%

Section: Aging Tests On Fpgasmentioning

confidence: 99%

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Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Huang

Wang

et al. 2022

Sensors

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“…In addition, these nine IRF-ETIs can cover 22 % of the entire chip. The node-selection algorithms for ageing detection are commonly based on the delay slacks of data paths in the design [Lai14,Ebr16c,Sad18]. We will refer to these algorithms as delay slack-based algorithms.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…In [Gom18], a critical-paths selection algorithm has been proposed for dynamic frequency scaling under BTI-ageing and process variations effects. A path selection flow for on-line ageing monitoring in reconfigurable architecture has been presented in [Ebr16c]. Their algorithm first selects the ageing-prone path based on path delay, temperature, duty cycle, and switching activity.…”

Section: Intermittent Fault Detection At Chip Levelmentioning

confidence: 99%

Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems

Ebrahimi¹

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A New Monitor Insertion Algorithm for Intermittent Fault Detection

Ebrahimi

Kerkhoff

2020

2020 IEEE European Test Symposium (ETS)

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The dependability of highly dependable systems relies on the reliability of its components and interconnections. One of the most challenging faults that threatens the reliability of interconnections in a system are intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months. As a result, evoking and detecting such faults is a major challenge. In this paper, IRF detection at the chip level has been tackled by utilising a fully digital insitu IRF monitor. This paper introduces a new algorithm for inserting IRF monitors in a design. The goal of this algorithm is to minimise the number of IRF monitors while providing a high fault coverage for IRFs. The algorithm has been validated using software-based fault injection. The simulation results show that the proposed algorithm improves the IRF coverage at the chip level at the cost of a small area and power-consumption overhead.

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Path Selection and Sensor Insertion Flow for Age Monitoring in FPGAs

Cited by 10 publications

References 15 publications

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems

A New Monitor Insertion Algorithm for Intermittent Fault Detection

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