Path smoothing via discrete optimization

Moffitt, Michael D.; Papa, David A.; Li, Zhuo; Alpert, Charles J.

doi:10.1145/1391469.1391655

Cited by 18 publications

(5 citation statements)

References 20 publications

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“…[20] improves the differential timing model from [3] using a pin-based timing LP formulation to reduce wirelength without timing degradation. [16] presents a discretized approach that uses branch-and-bound to choose the location of cells.…”

Section: Related Workmentioning

confidence: 99%

“…Equations (14) and (15) make sure that cells do not overlap. Finally, Equation (16) specifies an upper bound Dmax for the displacement of a cell from its original location (x 0 j , y 0 j ). This constraint ensures that TDP maintains a cell distribution similar to the one obtained by global placement, which is a desirable feature [26] [11].…”

Section: Problem Formulationmentioning

confidence: 99%

“…Finally, (20) defines late and early arrival times for each cell, as already presented in Section 3.1. The objective function (17) is also subject to legality and maximum displacement constraints (10) to (16).…”

Section: Lagrangian Relaxation Formulationmentioning

confidence: 99%

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Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

Guth

Livramento

Netto

et al. 2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

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Timing-driven placement (TDP) finds new legal locations for standard cells so as to minimize timing violations while preserving placement quality. Although violations may arise from unmet setup or hold constraints, most TDP approaches ignore the latter. Besides, most techniques focus on reducing the worst negative slack and let the improvements on total negative slack as a secondary goal. However, to successfully achieve timing closure, techniques must also reduce the total negative slack, which is known as slack histogram compression. This paper proposes a new Lagrangian Relaxation formulation for TDP to compress both late and early slack histograms. To solve the problem, we employ a discrete local search technique that uses the Lagrange multipliers as net-weights, which are dynamically updated using an accurate timing analyzer. To preserve placement quality, our technique uses a small fixed-size window that is anchored in the initial location of a cell. For the experimental evaluation of the proposed technique, we relied on the ICCAD 2014 TDP contest infrastructure. The results show that our technique significantly reduces the timing violations from an initial global placement. On average, late and early total negative slacks are improved by 85.03% and 42.72%, respectively, while the worst slacks are reduced by 71.55% and 34.40%. The overhead in wirelength is less than 0.1%.

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Section: Related Workmentioning

confidence: 99%

Section: Problem Formulationmentioning

confidence: 99%

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Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

Guth

Livramento

Netto

et al. 2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

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“…EXTENSIONS SPIRE's key advantage over existing physical synthesis transformations is the synergistic use of several types of optimizations. Our MILPs are more costly than existing transformations but also more powerful since they can be applied to larger windows than many of the localized transformations used in the industry today [11], [12]. This flexibility of SPIRE allows one to change the size and scope of optimization and offers rich trade-off opportunities.…”

Section: Cloning To Increase the Scope Of Retimingmentioning

confidence: 99%

SPIRE: A retiming-based physical-synthesis transformation system

Papa¹,

Krishnaswamy²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-The impact of physical synthesis on design performance is increasing as process technology scales. Current physical synthesis flows generally perform a series of individual netlist transformations based on local timing conditions. However, such optimizations lack sufficient perspective or scope to achieve timing closure in many cases. To address these issues, we develop an integrated transformation system that performs multiple optimizations simultaneously on larger design partitions than existing approaches. Our system, SPIRE, combines physically-aware register retiming, along with a novel form of cloning and register placement. SPIRE also incorporates a placement-dependent static timing analyzer (STA) with a delay model that accounts for buffering and is suitable for physical synthesis. Empirical results on 45nm microprocessor designs show 8% improvement in worstcase slack and 69% improvement in total negative slack after an industrial physical synthesis flow was already completed.

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“…(a) global timing-driving placement techniques [21,24,26,29,33,37,51,54,56,74], and (b) incremental timing-driven placement techniques [14,16,17,40,41, 73].…”

Section: Introductionmentioning

confidence: 99%

Placement techniques for the physical synthesis of nanometer-scale integrated circuits

Viswanathan¹

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Path smoothing via discrete optimization

Cited by 18 publications

References 20 publications

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

SPIRE: A retiming-based physical-synthesis transformation system

Placement techniques for the physical synthesis of nanometer-scale integrated circuits

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