PATIS: Using partial configuration to improve static FPGA design productivity

Frangieh, T.; Chandrasekharan, A.; Rajagopalan, Sundararaman; Iskander, Yousef; Craven, Stephen; Patterson, Cameron

doi:10.1109/ipdpsw.2010.5470755

Cited by 9 publications

(6 citation statements)

References 3 publications

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“…Finally, agility is defined as the ease and efficiency at which modifications can be made to a design. It is a common occurrence during FPGA development that a trivial change requires a re-implementation of the entire design, a lengthy process taking potentially tens of hours for large designs [20]. Software build tools such as Make selectively rebuild only the affected units within the dependency tree of the modified unit.…”

Section: Discussionmentioning

confidence: 99%

“…Even with modular and incremental flows, a seemingly small change may still require a full re-implementation. The PATIS project [20] discussed in Section 4.3.1 addresses this problem.…”

Section: Fpga Developmentmentioning

confidence: 99%

“…GHz Intel Core i7-920 processor, targeting an XC4VFX100 part [20]. Blank table entries represent implementations that did not produce a result after 30 hours and that were terminated.…”

Section: Commercial Debug Solutionsmentioning

confidence: 99%

See 2 more Smart Citations

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Iskander

Patterson

Craven

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs.The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger.This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.

show abstract

Section: Discussionmentioning

confidence: 99%

“…Even with modular and incremental flows, a seemingly small change may still require a full re-implementation. The PATIS project [20] discussed in Section 4.3.1 addresses this problem.…”

Section: Fpga Developmentmentioning

confidence: 99%

See 1 more Smart Citation

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Iskander

Patterson

Craven

2011

2011 21st International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

show abstract

“…The closest related work [10] presents a dynamic modular design flow based on partial reconfiguration to improve static or design-time productivity. The main ideas are to combine a dynamically automatic and speculative floorplanner with the design reuse methodology provided by the partial reconfiguration flow.…”

Section: Related Workmentioning

confidence: 99%

Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems

Muench

Paulitsch

Honold

et al. 2014

2014 17th Euromicro Conference on Digital System Design

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The design and operation of an aircraft, a railway, and a nuclear power station that include either safety-critical or safety-related systems require a proof that its safety is assured. The process providing this proof is called certification. This paper suggests an iterative FPGA implementation and iterative certification concept for FPGA-based systems to provide design-time adaptability while the complexity is still kept low to ease certification.The practical evaluation of this concept demonstrates that reuse at implementation level of a previously implemented part is to 100% usable for iterative certification. Regarding the resource utilization and complexity, the evaluation shows that there are potential savings in resource utilization and complexity compared to conventional run-time configurable designs. Iterative certification reduces the recertification of a whole design to a recertification of the changed part only and a verification tool qualification. It is shown that tool qualification can be accomplished with relatively moderate effort. Therefore, the presented concept substantially eases the certification process when using modular design and building block reuse.

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“…Besides the ability to design the entire static design of an FPGA in a simpler and faster way, by means of abstract structures, it is possible to achieve peculiar capabilities, such as partial dynamic reconfiguration. Partial reconfiguration is an advanced technique that allows one to change the configuration of a FPGA at runtime [18,19]. The dynamic reconfiguration of systems, which uses functionality to replace configuration data without interrupting its operation, has been provided for many years [20].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

et al. 2018

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Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration technique can be used to enable energy efficiency in a generic IoT node that exploits a Field Programmable Gate Array (FPGA) device. Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices. Exploiting the ability of reconfiguring circuit portions at runtime, the latest generation of FPGAs can be used to foster a better balance between energy consumption and performance. More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard. To this aim, a case study of a video filtering system is proposed and analyzed by dynamically loading three different hardware filters from the management software running on a Linux-based device. With more details, the presented analytical framework allows for a direct comparison between the energy efficiency of a dynamic partially reconfigurable device and a static non-reconfigurable one. The estimated timing conditions that allow the dynamic partially reconfigurable process to achieve relevant energy efficiency with respect to the corresponding static architecture are also outlined.

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PATIS: Using partial configuration to improve static FPGA design productivity

Cited by 9 publications

References 3 publications

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

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