Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis

Shi, Jin; Cai, Yici; Tan, Sheldon X.-D.; Fan, Jeffrey; Hong, Xianlong

doi:10.1109/tcad.2007.892337

Cited by 14 publications

(11 citation statements)

References 8 publications

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“…Errors would occur due to the inaccuracy of I * Bi s. In Step 3 (called error reduction step), those errors are computed and fed back to the original grid to solve for the correction components. Instead of using the block Jacobi iteration process in [Shi et al 2007], the analysis schemes in Step 1 and Step 2 are employed to correct the circuit responses. It can be shown that by including…”

Section: K)mentioning

confidence: 99%

“…After obtaining the full system solution, residues are computed and set as the new current loadings to the original grid to form a correction grid. Unlike the traditional block Jacobi iteration scheme [Shi et al 2007], which always sets boundary currents to zero in the error correction grid, the proposed process employs the boundary currents approximation scheme in Step 1 to provide a large coupling region to obtain more accurate boundary currents, thus reduce the errors more rapidly. Then the correction components of node voltages are computed in Step 2.…”

Section: Block Based Iterative Error Reductionmentioning

confidence: 99%

See 1 more Smart Citation

Locality-Driven Parallel Static Analysis for Power Delivery Networks

Zeng¹,

Feng

Li³

et al. 2011

ACM Trans. Des. Autom. Electron. Syst.

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Large VLSI on-chip power delivery networks (PDN) are challenging to analyze due to the sheer network complexity. In this paper, a novel parallel partitioning based PDN analysis approach is presented. We use the boundary circuit responses of each partition to divide the full grid simulation problem into a set of independent sub grid simulation problems. Instead of solving exact boundary circuit responses, a more efficient scheme is proposed to provide near exact approximation to the boundary circuit responses by exploiting the spatial locality of the flip-chip type power grids. This scheme is also used in a block based iterative error reduction process to achieve fast convergence. Detailed computational cost analysis and performance modeling is carried out to determine the optimal (or near optimal) number of partitions for parallel implementation. Through the analysis of several large power grids, the proposed approach, is shown to have excellent parallel efficiency, fast convergence, and favorable scalability. Our approach can solve a 16 million-node power grid in 18 seconds on an IBM p5-575 processing node with 16 Power5+ processors, which is 18.8X faster than a state of the art direct solver.

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Section: K)mentioning

confidence: 99%

Section: Block Based Iterative Error Reductionmentioning

confidence: 99%

Locality-Driven Parallel Static Analysis for Power Delivery Networks

Zeng¹,

Feng

Li³

et al. 2011

ACM Trans. Des. Autom. Electron. Syst.

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“…In our problem, we need to represent the log-normal random variable by using the Hermite PC expansion form (22) where . To find the other coefficients, we can apply (9) on .…”

Section: A Hermite Pc Representation Of Log-normal Variablesmentioning

confidence: 99%

“…On-chip power grid analysis and designs have been intensively studied in the past due to the increasing impacts of excessive voltage drops as technologies scale [2], [4], [11], [14], [21], [22], [25], [26], [29], [30], [32]. Owning to the increasing impacts of leakage currents and its variations on the circuit performances, especially on the on-chip power delivery networks, a number of research works have been proposed recently to perform the stochastic analysis of power grid networks under process-induced leakage current variations.…”

mentioning

confidence: 99%

Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation

Fan

Tan

et al. 2008

IEEE Trans. Circuits Syst. I

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As the technology scales into 90 nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the voltage drop variations of on-chip power grid networks, considering log-normal leakage current variations with spatial correlation. The new analysis is based on the Hermite polynomial chaos (PC) representation of random processes. Different from the existing Hermite PC based method for power grid analysis (Ghanta et al., 2005), which models all the random variations as Gaussian processes without considering spatial correlation, the new method consider both wire variations and subthreshold leakage current variations, which are modeled as log-normal distribution random variables, on the power grid voltage variations.To consider the spatial correlation, we apply orthogonal decomposition to map the correlated random variables into independent variables. Our experiment results show that the new method is more accurate than the Gaussian-only Hermite PC method using the Taylor expansion method for analyzing leakage current variations. It is two orders of magnitude faster than the Monte Carlo method with small variance errors. We also show that the spatial correlation may lead to large errors if not being considered in the statistical analysis.Index Terms-Hermite polynomials, leakage current, power delivery network, spectral analysis.

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“…Methods such as multigridlike [1,5], hierarchical [16,2], partition-based [3], fast iterative [13] and random walk based [12,4] approaches help improve scalability of power gird network analysis. Another * This work is supported in part by NSF CAREER Award under grant CCF-0448534, and UC Micro Program #06-252 and #07-105 via Cadence Design System Inc.…”

Section: Introductionmentioning

confidence: 99%

ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis

Li¹,

Tan²,

McGaughy³

2008

2008 Design, Automation and Test in Europe

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In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model order reduction techniques to reduce the circuit matrices before the simulation. Different from the (improved) extended Krylov subspace methods EKS/IEKS [15,2], ETBR performs fast truncated balanced realization on response Grammian to reduce the original system with the similar computation costs of EKS. ETBR also avoids the adverse explicit moment representation of the input signals. Instead, it uses spectrum representation of input signals by fast Fourier transformation. As a result, ETBR is more flexible for different types of input sources and can better capture the high frequency contents than EKS, and this leads to more accurate results especially for fast changing input signals. Experimental results on a number of large networks (up to one million nodes) show that, given the same order of the reduced model, ETBR is indeed more accurate than the EKS method especially for input sources rich in high-frequency components. ETBR also shows similar computation costs of EKS and less memory consumption than EKS.

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Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis

Cited by 14 publications

References 8 publications

Locality-Driven Parallel Static Analysis for Power Delivery Networks

Locality-Driven Parallel Static Analysis for Power Delivery Networks

Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation

ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis

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