Pattern Generation Research of BIST Based on Low Power

Abstract

In this paper, a new BIST structure is presented, which is generated by the LFSR modified. There is no redundant single input jump test incentive, all possible test vector combinations are covered, the testing power is reduced. Moreover, the testing time do not increase and fault-coverage rate won't be affected. Experiment results on the integrated circuit 74HC42 show that the switching activity reduction can be achieved up to 64% while achieving high fault coverage, especially suitable for BIST of Integrated circuits.