Patterned wafer geometry grouping for improved overlay control

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Junbeom, Park; Song, Chonghui; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Chung‐Che; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

doi:10.1117/12.2257834

Cited by 2 publications

(4 citation statements)

References 4 publications

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“…where r denotes the distance between the center and the edge of the wafer. In this work, different wafer bows when depositing different thicknesses of PE TEOS and HDP oxide in 12 inch wafers are measured by KLA Tencor PWG tool [23,24].…”

Section: Measurementmentioning

confidence: 99%

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Hong¹,

Xu²,

Hou³

et al. 2021

Semicond. Sci. Technol.

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In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced Tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer.In our experiments, both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We investigate the mechanism of PE TEOS oxide pitting and silicon nitride corroding, and propose two solutions: 1) HDP oxide + PE TEOS, and 2) PE TEOS + dry etching.Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.

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Section: Measurementmentioning

confidence: 99%

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Hong¹,

Xu²,

Hou³

et al. 2021

Semicond. Sci. Technol.

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“…As the manufacturing process continues, stacked films with different levels of non-uniform residual stress induce overlay error, which we call process-induced overlay error. In many papers, process-induced overlay error has always been emphasized as a critical issue in OPO control [1,3,4,5]. Particularly, process-induced overlay errors in 3D NAND devices appear as the number of stacked layers increases accompanying non-uniform residual stress [6].…”

Section: Introductionmentioning

confidence: 99%

“…The PWG tool is suitable for high-volume manufacturing (HVM) process monitoring due to its high throughput for inline measurements that drive timely process corrections. There have been previous publications describing process-induced overlay error with PWG data-based metrics and applications to monitor and control OPO [5,7,8,1,3,9,4,10]. In-plane distortion (IPD) is a representative metric that estimates process-induced overlay errors.…”

Section: Introductionmentioning

confidence: 99%

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Device overlay root cause process detection using patterned wafer geometry information

Ham,

Song,

Lee

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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On-product overlay (OPO) is a critical inline process control parameter in semiconductor manufacturing. One of the main factors that induce the overlay error is non-lithography processes like etching, deposition and cleaning. The overlay margin is getting tighter as the device technology advances and detecting the root cause of process-induced overlay error is a main problem to improving the OPO. However, it is not an easy problem to solve due to the lack of inline monitoring data on non-lithography processes. Even if we evaluate inline monitoring data, it is too sparse to do in-depth analysis compared to abundant lithographic overlay data. Instead, we can make use of data from the PWG™ patterned wafer geometry metrology system, which can measure high-density data with high throughput. In this paper, we introduce a comprehensive method of detecting the root cause of the process-induced overlay errors based on inline PWG data. Our target device is a 3D NAND product with process-induced overlay errors due to wafer geometry. We start our analysis by tracing PWG GEN3 data for the same wafer in a wide process step range. We compare the GEN3 signature to an overlay error signature of a target lithography layer to filter out suspicious processes. From the suspicious processes, we derived optimized KPIs that discriminate between good and bad wafers in terms of process-induced overlay errors, which are then used as a monitoring metric. With the optimized KPIs, we discern which process is the root cause of process-induced overlay errors to help drive corrective actions and improve OPO on the target device. Finally, we propose a comprehensive framework that is not limited to PWG data but applies to other available inline data such as alignment, ADI and AEI overlay and NZO.

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Patterned wafer geometry grouping for improved overlay control

Cited by 2 publications

References 4 publications

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Device overlay root cause process detection using patterned wafer geometry information

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