2014
DOI: 10.1116/1.4867357
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Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

Abstract: International audienc

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Cited by 17 publications
(12 citation statements)
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References 31 publications
(32 reference statements)
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“…9 Blanc et al showed that improved spacer process performance can be obtained by using synchronous pulsed plasma technology. 10 The switching on and off in a synchronous manner of both the source and bias powers at a low duty cycle allows us to decrease the average ion energy and the plasma chemical reactivity (more molecular than atomic), which ultimately reduce plasma induced damage. Although they showed that pulsed plasma process leads to minimized silicon recess and improved spacer profiles compared to CW plasma processes, the spacer process performance is still not satisfactory for advanced technology nodes.…”
Section: Introductionmentioning
confidence: 99%
“…9 Blanc et al showed that improved spacer process performance can be obtained by using synchronous pulsed plasma technology. 10 The switching on and off in a synchronous manner of both the source and bias powers at a low duty cycle allows us to decrease the average ion energy and the plasma chemical reactivity (more molecular than atomic), which ultimately reduce plasma induced damage. Although they showed that pulsed plasma process leads to minimized silicon recess and improved spacer profiles compared to CW plasma processes, the spacer process performance is still not satisfactory for advanced technology nodes.…”
Section: Introductionmentioning
confidence: 99%
“…It has been shown that the addition of C 4 F 8 in SF 6 plasma results in the reduction of available F species and increases the deposition rate of passivation film [13]. Even if inductively coupled plasma (ICP) technique is standardly used in industry for the etching of nanometric Si 3 N 4 spacers using fluorocarbon-based processes [4], etching processes of ultrashallow Si 3 N 4 nanostructures are really scarce in the literature.…”
Section: Introductionmentioning
confidence: 99%
“…In complementary metal-oxide-semiconductor (CMOS) technology, a precise Si 3 N 4 etching control and a high selectivity are required for applications such as gate spacers [4] or shallow trench isolation [5], where overetch needs to be damage-less for the underlying films or devices. In the fabrication of nanodevices, controllable slow etch rates are more and more demanded for the etching of thin films.…”
Section: Introductionmentioning
confidence: 99%
“…Silicon nitride (SiN x ) thin films are dielectric materials that play an important role in the semiconductor industry. By varying the silicon/nitrogen composition or deposition methods, such films can serve as passivation layers in device packaging, 1,2 insulators of interconnects in Back End of Line (BEOL), 3 gate spacers for high mobility channel transistor fabrication 4 and more. 5 Silicon oxynitrides (SiO x N y ) are also essential materials in the semiconductor industry 6 as a dielectric layer and for integrated optics and waveguides.…”
Section: Introductionmentioning
confidence: 99%