PBTI-Induced Random Timing Jitter in Circuit-Speed Random Logic

Abstract

Accurate reliability predictions of real-world digital logic circuits rely heavily on the relevancy of device-level testing. In the case of bias temperature instability (BTI), where recovery plays a significant role, a leap of faith is taken to translate device-level reliability data into a practical information for the real-world circuit implications. In this paper, we develop a methodology to bridge this gap by employing an eye diagram approach, which allows us to monitor, at circuit speed, device-level random jitter degradation in response to stress. By employing a variety of positive BTI gate voltage stress and sense bit sequences (including dc, ring oscillator (RO), and pseudorandom), we are able to compare the effectiveness of these approaches at capturing random timing jitter. We find that conventional RO-type measurements are unable to capture the random jitter degradation. This calls into question the effectiveness of using RO structures as a proxy for real-random logic circuits. Only when a pseudorandom bit sequence is employed does the true extent of jitter degradation become observable. This is an important development and serves as an accurate means to translate device-level reliability data to predict real-world digital logic circuit degradation.Index Terms-Jitter, positive bias temperature instability (PBTI), pseudorandom bit sequence (PRBS).

Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes

“…where W is channel width, C ox is the oxide capacitance, and V T is the threshold voltage of the transistor [25]. Using the temperature dependent backscattering model, B sat can be obtained from ratio of the near-equilibrium mean-free path λ 0 over the critical distance l 0 over which the potential drops by k B T from the peak of the conduction band barrier, as illustrated in the Fig.…”

“…Fig. 3(c) shows the schematic structure of setup for sub-1 ns electrical characterization based on the ultra-fast measurement system in [24], [25]. Here, the device under test (DUT) is designed for RF-level high-speed measurements.…”

Device-level jitter as a probe of ultrafast traps in high-k MOSFETs

“…It was shown earlier [1,2] that a sequence of pulses of fixed width fired with fixed duty cycle, i.e. a signal pattern generated by a ring oscillator (RO), commonly used for jitter evaluation, does not allow one to confidently measure stress-related increase of jitter in a MOSFET.…”

“…Previously, we developed a methodology to measure the jitter of a single device at realistic circuit speeds in response to BTI stress [1,2]. In this study, we apply similar techniques to probe fast electron traps (defects in the gate stack) in Si/high-k nMOSFETs.…”