PCB via to trace return loss optimization for &gt;25Gbps serial links

Zhang, Ji; Lim, Jane; Yao, Wei; Qiu, Kelvin; Brooks, Richard R.

doi:10.1109/isemc.2014.6899045

Cited by 16 publications

(3 citation statements)

References 3 publications

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“…It can be concluded from Equations ( 11) and ( 12), the width of the reference plane W, the number of vias on the reference plane k and the diameter of vias VD will affect the resonant frequency of the transmission line. The change of the number of vias k is actually changing the center distance VVL between the connected vias [23,24].…”

Section: Research On Transmission Line Reference Plane For 25 Gbps Ra...mentioning

confidence: 99%

Optimization and Design of Passive Link with Single Channel 25 Gbps Based on High-Speed Backplane

Liu

Zhang

et al. 2021

Electronics

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In recent years, with the development of the communication industry, the need to use Ethernet switches to transmit big data has become more urgent, and its protocol standards are iterating towards higher return loss, wider bandwidth, lower impedance fluctuations and insertion loss. Based on the research of high-speed backplane with a single channel 25 Gbps transmission rate, a novel double grounded planar strip coplanar waveguide design is presented, which significantly improved return loss to 20 dB and reduced insertion loss, which meet the loss standard of 100GBASE-KR4. The resonant cavity model of transmission line reference plane is improved by introducing vias and the parameters of vias in the reference plane are studied to reduce the impact of resonance, which improved the transmission –1 dB bandwidth to 60 GHz. Based on equivalent circuit analysis of differential vias’ joint reverse pad, the parameters related to the differential vias are studied, the impedance fluctuation is reduced to 100 ± 3 Ω, which is 70% better than the impedance fluctuation standard (100 ± 10 Ω) of 100GBASE-KR4. After optimizing the mathematical model of strip coplanar waveguide, reference plane and differential vias, we built a simulation model of the backplane passive link which met the 100GBASE-KR4 backplane Ethernet specification. In the actual test, it was found that the optimized model can improve the link performance.

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Section: Research On Transmission Line Reference Plane For 25 Gbps Ra...mentioning

confidence: 99%

Optimization and Design of Passive Link with Single Channel 25 Gbps Based on High-Speed Backplane

Liu

Zhang

et al. 2021

Electronics

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“…In (VASA et al, 2018), common designer errors in the optimization of impedance of vias are discussed. In (ZHANG et al, 2014), the addition of transition lines with slightly lower impedance in relation to the vias is proposed to compensate for the capacitive and inductive discontinuities generated by the vias. In (LEE; HIRSCH; BELL, 2018), the optimization of vias using the frequency domain reflected impedance (Z11) is proposed instead of the time domain reflected impedance (TDR) optimization.…”

Section: Introductionmentioning

confidence: 99%

High Sensitivity Envelope Detector Assisted by Microwave Photonics

Gonçalves¹,

Ivo²,

Coutinho³

2022

Smart Systems: Theory and Advances

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Theory and Advances is licensed under CC BY 4.0.This license requires that reuses give credit to the creator. It allows reusers to distribute, remix, adapt, and build upon the material in any medium or format, even for commercial purposes.The content of the work and its data in its form, correctness and reliability are the sole responsibility of the authors, and do not represent the official position of Amplla Publishing. Downloading and sharing of the work is permitted as long as credit is given to the authors. All rights to this edition were ceded to Editora Amplla.

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“…To achieve it, application-specific integrated circuit (ASIC) with integrated multi-gigabit high speed serial link transceivers is widely used due to the advantage of its high performance and high reliability, small volume and light weight, and relative low power consumption [2]. Standards such as OIF CEI-25G, CEI-28G and 32G-FC [3], [4] require those transceivers to operate at high data rates over imperfect channels with extra insertion loss, impedance discontinuities [5], [6], power supply noises, and the crosstalk. Among those difficult signal integrity challenges, SerDes pin-out induced PCB via crosstalk has become a significant source of high jitter and has the potential to become a dominant design consideration.…”

Section: Introductionmentioning

confidence: 99%

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Yao

Lim

et al. 2015

2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity

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Fast growing bandwidth demands for networking and data center applications continuously face difficult signal integrity challenges. Among them, serializer/deserializer (SerDes) package pin-out and its corresponding printed circuit board (PCB) via crosstalk have become a significant source of high jitter and limit the performance of high speed serial links. In this paper, a variety of far-end crosstalk (FEXT) and nearend crosstalk (NEXT) SerDes pin-out patterns are designed and investigated to explore the crosstalk performance for interfaces running 25Gb/s and beyond. The impact of PCB routing layer selection and via stub are also considered. Both frequency domain and time domain analysis are studied based on 3-dimensional (3D) full wave electromagnetic (EM) simulation, and the results are compared along with the calculated integrated crosstalk noise (ICN) to find the pattern with better signal isolation. A PCB test vehicle is designed and manufactured to provide measurement and verification results by using broadband micro-probes and multi-port vector network analyzer (VNA). The optimized pinout is then selected to evaluate the overall link performance based on the input/output buffer information specification algorithmic modeling interface (IBIS-AMI) model from silicon vendors.

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PCB via to trace return loss optimization for >25Gbps serial links

Cited by 16 publications

References 3 publications

Optimization and Design of Passive Link with Single Channel 25 Gbps Based on High-Speed Backplane

Optimization and Design of Passive Link with Single Channel 25 Gbps Based on High-Speed Backplane

High Sensitivity Envelope Detector Assisted by Microwave Photonics

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

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PCB via to trace return loss optimization for >25Gbps serial links

Cited by 16 publications

References 3 publications

Optimization and Design of Passive Link with Single Channel 25 Gbps Based on High-Speed Backplane

Optimization and Design of Passive Link with Single Channel 25 Gbps Based on High-Speed Backplane

High Sensitivity Envelope Detector Assisted by Microwave Photonics

Design of package BGA pin-out for &#x003E;25Gb/s high speed SerDes considering PCB via crosstalk

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Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk