2006
DOI: 10.1063/1.2335677
|View full text |Cite
|
Sign up to set email alerts
|

Pd-nanocrystal-based nonvolatile memory structures with asymmetric SiO2∕HfO2 tunnel barrier

Abstract: A thickness modulation effect of Hf O 2 interfacial layer between double-stacked Ag nanocrystals for nonvolatile memory device applications

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
31
0

Year Published

2007
2007
2021
2021

Publication Types

Select...
8

Relationship

0
8

Authors

Journals

citations
Cited by 59 publications
(31 citation statements)
references
References 14 publications
0
31
0
Order By: Relevance
“…The multilayer ͑or stacked͒ tunnel layer concept such as high-k / SiO 2 or SiO 2 / high-k / SiO 2 structures seems to be a promising solution due to the redistribution of electric field across the tunnel stack compared with a single tunnel layer, making the tunnel layer thinner at the same applied bias. [3][4][5][6][7][8][9] The stacked tunnel layer structure can therefore result in a better P/E efficiency while maintaining sufficient charge retention at the same time.…”
mentioning
confidence: 99%
“…The multilayer ͑or stacked͒ tunnel layer concept such as high-k / SiO 2 or SiO 2 / high-k / SiO 2 structures seems to be a promising solution due to the redistribution of electric field across the tunnel stack compared with a single tunnel layer, making the tunnel layer thinner at the same applied bias. [3][4][5][6][7][8][9] The stacked tunnel layer structure can therefore result in a better P/E efficiency while maintaining sufficient charge retention at the same time.…”
mentioning
confidence: 99%
“…Most of the studies, including ours, have focused on the fabrication of metal-oxide-semiconductor ͑MOS͒ structures having semiconductor NCs. [5][6][7][8] Nevertheless, MOS-based memory devices fabricated with metal NCs, like Au, 9 Ni, [9][10][11] Ru, 12 W, 13 Pd, 14 RuO x , 17 TiN, 18 etc., are considered to be more advantageous for their higher density of states around the Fermi level, a wide range of available work function, stronger coupling with conduction channels, and smaller energy perturbation due to carrier confinement, [19][20][21][22] with the semiconductor counterpart. The use of metal NCs also makes it possible to use smaller operating voltages while obtaining better endurance characteristics and faster write/erase speeds with smaller fluctuations and interface states due to its high work function in comparison to its semiconductor counterpart.…”
mentioning
confidence: 99%
“…[1][2][3][4][5][6][7][8][9][10][11][12][13][14] Embedded NCs in the floating gate sandwiched between tunnel and control oxide layers are charged by direct-tunnel electrons from the channel to shift the device threshold.…”
mentioning
confidence: 99%
“…However, there are lots of key points needed to be solved prior to the practical applications, especially, including the trade-off between long retention time and high programming speed. The stacked heterostructures, such as semiconductor hetero-nanocrystals (Ge/Si, silicide/Si) [6][7][8][9][10] or stacked dielectrics [11,12], are considered as a most hopeful way to overcome the above-mentioned contradictory problem, where the combination of different band-gaps causes the injected charge well stored in the side of lower band energy.…”
mentioning
confidence: 99%