2010 International SoC Design Conference 2010
DOI: 10.1109/socdc.2010.5682930
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Peak power reduction methodology for multi-core systems

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Cited by 19 publications
(11 citation statements)
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“…Some related works focused on minimizing the peak power consumption under real-time constraints [1][13] [64]. Lee et al [1] have proposed a new scheduling algorithm for realtime tasks to minimize chip-level power consumption, without relying on any extra hardware (e.g., DVFS controller).…”
Section: B Peak-power Managementmentioning
confidence: 99%
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“…Some related works focused on minimizing the peak power consumption under real-time constraints [1][13] [64]. Lee et al [1] have proposed a new scheduling algorithm for realtime tasks to minimize chip-level power consumption, without relying on any extra hardware (e.g., DVFS controller).…”
Section: B Peak-power Managementmentioning
confidence: 99%
“…This work restricts the concurrent execution of tasks that are assigned to different cores. Lee et al [64] has proposed a task scheduling that prevents the occurrence of the peak power consumption for task-graph models. The proposed algorithm in [64] schedules the tasks, considering data dependency information while reducing the peak power.…”
Section: B Peak-power Managementmentioning
confidence: 99%
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“…The problem is important in both embedded [16][17][18] as well as super-computing domain [19,20]. The authors in [21] propose an algorithm to minimize peak power for an application with a task graph without a deadline. The authors of [22] were the first to study the problem of peak power minimization in the context of task graph-based many-core applications with a deadline.…”
Section: Related Workmentioning
confidence: 99%
“…In this situation, the execution of all LC and HC tasks requires higher computational demands, which may exceed the processor's capacity, and the system becomes overloaded [6]. Thus, all cores may execute tasks simultaneously to meet deadlines of tasks, which increase the instantaneous processor power beyond its Thermal Design Power (TDP) constraint [7]- [9]. TDP is the maximum sustainable power that a chip can dissipate safely.…”
Section: Introductionmentioning
confidence: 99%