PEAS-III: an ASIP design environment

Itoh, Makiko; Higaki, S.; Sato, Jun; Takeuchi, Yoshinori; Kitajima, Akira; Imai, Masayuki

doi:10.1109/iccd.2000.878319

Cited by 79 publications

(30 citation statements)

References 2 publications

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“…PEAS-III [13], EXPRESSION [14], LISA [15], MADL [16], RDLC [17], and many others use architecture description languages (ADLs) to allow designers to build a specific processor or explore a design space. However, we notice three main drawbacks in these approaches for our purposes: 1) The verbose processor descriptions severely limit the speed of design space exploration.…”

Section: A Related Workmentioning

confidence: 99%

Exploration and Customization of FPGA-Based Soft Processors

Yiannacouras

Steffan

Rose

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-As embedded systems designers increasingly use field-programmable gate arrays (FPGAs) while pursuing single-chip designs, they are motivated to have their designs also include soft processors, processors built using FPGA programmable logic. In this paper, we provide: 1) an exploration of the microarchitectural tradeoffs for soft processors and 2) a set of customization techniques that capitalizes on these tradeoffs to improve the efficiency of soft processors for specific applications. Using our infrastructure for automatically generating soft-processor implementations (which span a large area/speed design space while remaining competitive with Altera's Nios II variations), we quantify tradeoffs within soft-processor microarchitecture and explore the impact of tuning the microarchitecture to the application. In addition, we apply a technique of subsetting the instruction set to use only the portion utilized by the application. Through these two techniques, we can improve the performance-per-area of a soft processor for a specific application by an average of 25%.Index Terms-Customization, design space exploration, field--programmable gate array (FPGA)-based soft-core processors, processor generator.

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Section: A Related Workmentioning

confidence: 99%

Exploration and Customization of FPGA-Based Soft Processors

Yiannacouras

Steffan

Rose

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…It allows modifications of data width, number of registers, depth of hardware task queue, and addition of custom functionality in Verilog. PEAS [50] is a GUI based hardware=software codesign framework. It generates HDL code along with software toolkit.…”

Section: Generation Of Hardware Implementationmentioning

confidence: 99%

“…Examples of processor template based approaches are Xtensa [40], Jazz [49] and PEAS [50]. Xtensa [40] is a scalable RISC processor core.…”

Section: Generation Of Hardware Implementationmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. The paper surveys the existing ADLs in terms of (a) the inherent features of the languages and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation and validation of programmable embedded systems. It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.

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“…Using parameterizing and organizing the whole units, a pipelined microprocessor can be automatically generated [2,3,4]. These studies are usually based on one particular architecture and rely on more manual design work, but with good performance.…”

Section: Introductionmentioning

confidence: 99%

A Method for Automatically Implementing FPGA-basedPipelined Microprocessors

Zeng¹,

Han²,

Jiang³

et al. 2017

Proceedings of the International Conference on Computer Networks and Communication Technology (CNCT 2016)

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Abstract. This paper presents a method of automatically generating the Verilog implementation of pipelined micro-processors. Based on the RTL descriptions of instructions, all types of hazards in pipelining are addressed optimally, especially in avoiding redundancy, reducing resource utilization and improving instruction throughput. Moreover, out-of-order execution mechanism is adopted in order to support multi-cycle instructions more efficiently. Besides, all the multiplexers and logics of control signals are analyzed and produced all by the method. The synthesized implementations of both pipelined controllers and datapaths are generated automatically, based on non-fixed architectures. A case study based on MIPS architecture not only explains the framework from input to simulation, but also illustrates the method gains almost equal performance with manual work.

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PEAS-III: an ASIP design environment

Cited by 79 publications

References 2 publications

Exploration and Customization of FPGA-Based Soft Processors

Exploration and Customization of FPGA-Based Soft Processors

Processor Description Languages

A Method for Automatically Implementing FPGA-basedPipelined Microprocessors

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