Pentium 4 processor package design and development

Hasan, A.; Sathe, A.; Wood, David; Viswanath, R.

doi:10.1109/ectc.2003.1216483

Cited by 7 publications

(4 citation statements)

References 1 publication

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“…However, an ever increasing power dissipation density has resulted in thermal management challenges. It is critically important to be able to accurately determine device temperatures in order to assess the reliability of new technologies, because temperature is one of the dominant drivers of device degradation and influences device performance [2][3][4][5][6][7]. Phonon transport at the nanoscale and at interfaces impacts how waste heat is transported away from the active region in devices.…”

Section: Introductionmentioning

confidence: 99%

A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution

Kuball

Pomeroy

2016

IEEE Trans. Device Mater. Relib.

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This is the author accepted manuscript (AAM). The final published version (version of record) is available online via IEEE at http://ieeexplore.ieee.org/document/7590091. Please refer to any applicable terms of use of the publisher. University of Bristol -Explore Bristol Research General rightsThis document is made available in accordance with publisher policies. Please cite only the published version using the reference above. Full terms of use are available: http://www.bristol.ac.uk/pure/about/ebr-termsAbstract-We review the Raman thermography technique, which has been developed to determine the temperature in and around the active area of semiconductor devices with submicron spatial and nanosecond temporal resolution. This is critical for the qualification of device technology, including for accelerated lifetime reliability testing and device design optimization. Its practical use is illustrated for GaN and GaAs based high electron mobility transistors, and opto-electronic devices. We also discuss how Raman thermography is used to validate device thermal models, as well as determining the thermal conductivity of materials relevant for electronic and opto-electronic devices.

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Section: Introductionmentioning

confidence: 99%

A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution

Kuball

Pomeroy

2016

IEEE Trans. Device Mater. Relib.

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“…For laminated organic substrate technology and components requiring high-power/high-current applications, a published work has identified a design limit related to joule heating in the substrate circuitry [19]. Future microprocessor designs will place increasing thermal challenges on the technology and will require further invention and development.…”

Section: Discussionmentioning

confidence: 99%

“…In the interim, design guidelines are based on limits as defined in recent literature. Intel's study of this effect in support of its Pentium 4 processor package designs recommends limiting the carrier temperature build-up to 1208C for areas outside the device shadow [19]. To maintain temperatures below this limit for their family of applications and as defined by their reliability studies, the maximum current densities allowable were 0.33 mA/lm 2 through any conductive feature.…”

Section: Current-induced Heating and Its Implications For Designmentioning

confidence: 99%

The evolution of build-up package technology and its design challenges

Blackshear

Cases²,

Klink

et al. 2005

IBM J. Res. & Dev.

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This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

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“…Consider the two primary thermal architectures, shown in Figs. 1 and 2, typically associated with flip-chip technology [6]. In Architecture I, a thermal interface material (TIM) is used to thermally couple a bare die device to a heat sink, and in Architecture II, the heat sink interfaces with an integrated heat spreader (IHS) through a TIM.…”

Section: A Thermal Impedance For Some Basic Flip-chip Thermal Architmentioning

confidence: 99%

Density factor approach to representing impact of die power maps on thermal management

Torresola

Chiu

Chrysler

et al. 2005

IEEE Trans. Adv. Packag.

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In the microelectronics industry, power has traditionally been the key driver for thermal management. Cooling solutions are typically rated in terms of their power dissipation capacity and efficiency. However, overall power is not the only parameter that affects thermal management. For instance, it is well-known that power density is also important (i.e., it is easier to cool 50 W uniformly distributed on a 20 20 mm die than the same power on a 10 10 mm die). Furthermore, even if the die size remains unchanged, nonuniform power distribution at the die level can create localized regions of high power density that require thermal management. This paper proposes a simple metric, density factor (DF ), to be used in conjunction with power for quantifying the impact of power density on a given thermal solution. The advantages, limitations, and applicability of this metric are discussed.

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Pentium 4 processor package design and development

Cited by 7 publications

References 1 publication

A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution

A Review of Raman Thermography for Electronic and Opto-Electronic Device Measurement With Submicron Spatial and Nanosecond Temporal Resolution

The evolution of build-up package technology and its design challenges

Density factor approach to representing impact of die power maps on thermal management

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