Perceptual Quality Preserving SRAM Architecture for Color Motion Pictures

Yueh, Wen; Cho, Minki; Mukhopadhyay, Saibal

doi:10.7873/date.2013.035

Cited by 3 publications

(3 citation statements)

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“…With an effort to limit such overheads, recent approaches exploit the tolerance to faults/approximations of many applications [33] and relax the requirement of 100% correctness. The main idea of such methods is the restricted use of robust but power hungry bit-cells and methods such as ECC to protect only the bits that play a more significant role in shaping the output quality [208] [107]. Few very recent approaches exist also that extend generic instruction sets with approximation features and specialized hardware units [58] [192] [164].…”

Section: Approximate Computing With Statistical Error Confinementmentioning

confidence: 99%

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Zheng¹,

Noll²,

Chattopadhyay³

2018

Computer Architecture and Design Methodologies

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This thesis is the result of my work as research assistant at the Institute for Communication Technologies and Embedded Systems (ICE) at the RWTH Aachen University. During this time I have been accompanied and supported by many people. It is my great pleasure to take this opportunity to thank them. My most sincere thanks go to my advisors, Prof. Anupam Chattopadhyay and Prof. Tobias Noll. Anupam has been extremely helpful and tremendously inspiring throughout my PhD study. Prof. Noll has been impressively knowledgeable while patient with my ideas and mistakes. Their thoughtful advices have greatly contributed to this work and influenced me for my future career. Special thanks go to my defense committee members, Prof. Andrei Vescan and Prof. Renato Negra for spending their time, offering oral exam, giving me feedback, and attending my defense session. Several colleagues in ICE and EECS have assisted and encouraged me during the past five years for my work and personal life. Among them I would like to show my deep appreciation to Ayesha Khalid, Zoltán Rákossy and Michael Meixner. Furthermore, I would like to thank my students

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Section: Approximate Computing With Statistical Error Confinementmentioning

confidence: 99%

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Zheng¹,

Noll²,

Chattopadhyay³

2018

Computer Architecture and Design Methodologies

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“…5. The video sign_irene contains blue and red colors that would be directly affected by the corruption of chroma data [5]. It shows that, truncating 5 LSB bits (2 LSBs of Cr and 3 LSBs of Cb) is an optimized trade-off between video quality and power saving.…”

Section: D-dash-iiimentioning

confidence: 99%

Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming

Chen

Edstrom

Chen

et al. 2016

Proceedings of the 2016 International Symposium on Low Power Electronics and Design

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Nowadays, people enjoy watching mobile videos more than ever and mobile video streaming contributes to the majority of the total mobile data traffic. However, due to the high power consumption of mobile video decoders, especially the on-chip memories, short battery life represents one of the biggest contributors to user dissatisfaction. Various mobile embedded memory techniques have been investigated to reduce power consumption and prolong battery life. Unfortunately, the existing hardware-level research suffers from high implementation complexity and large overhead. In this paper, by introducing advanced data-mining techniques, we investigate meaningful data patterns hidden in mobile video data and apply the identified patterns to implement a low-power flexible hardware design with dynamic power-quality trade-off. A 45nm 32kb SRAM is presented that enables three levels of power-quality trade-off (up to 43.7% power savings) with negligible area overhead (0.06%). CCS Concepts• Hardware ➝ Semiconductor memory and Circuit power issues KeywordsMobile video streaming, on-chip memory, data mining, power efficient, dynamic trade-off.

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“…With an effort to limit such costs, recent approaches exploit the tolerance to faults/approximations of many applications [7] and relax the condition of 100% correctness. The main idea of such methods is the restricted use of robust but power-hungry bit-cells and techniques such as ECC to protect only the bits that play a more significant role in shaping the output quality [8,9]. Another group of approaches extend general instruction sets with approximation features and specialized hardware units [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

Shao

Wang

et al. 2019

Applied Sciences

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Nanoscale CMOS technology has encountered severe reliability issues especially in on-chip memory. Conventional word-level error resilience techniques such as Error Correcting Codes (ECC) suffer from high physical overhead and inability to correct increasingly reported multiple bit flip errors. On the other hands, state-of-the-art applications such as image processing and machine learning loosen the requirement on the levels of data protection, which result in dedicated techniques of approximated fault tolerance. In this work, we introduce a novel error protection scheme for memory, based on feature extraction through Principal Component Analysis and the modular-wise technique to segment the data before PCA. The extracted features can be protected by replacing the fault vector with the averaged confinement vectors. This approach confines the errors with either single or multi-bit flips for generic data blocks, whilst achieving significant savings on execution time and memory usage compared to traditional ECC techniques. Experimental results of image processing demonstrate that the proposed technique results in a reconstructed image with PSNR over 30 dB, while robust against both single bit and multiple bit flip errors, with reduced memory storage to just 22.4% compared to the conventional ECC-based technique.

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Perceptual Quality Preserving SRAM Architecture for Color Motion Pictures

Cited by 3 publications

References 0 publications

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming

A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

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