Performance Analysis for Clock and Data Recovery Circuits under Process Variation

Abstract

Clock and data recovery circuits play a very important role in modern data communication systems. It has very wide application in many areas, such as optical communications and interconnection between chips [1]. Today in IC industry, the shrinkage of feature size increasingly enlarges the uncertainty of circuit performance caused by process variation. As the data transmission speed dramatically increases, this uncertainty will heavily affect the clock and data recovery circuit performance and reliability in communication systems. Thus, research on performance variation of a clock and data recovery circuit caused by process variation is meaningful. The conclusion will have significant influence on chip testing. Firstly and most importantly, I am very grateful to my advisor, Dr. Wen-Ben Jone, for his valuable guidance and encouragement. Without him, I could not have worked on this research smoothly. For this research, his time and efforts deserve the most credit. Secondly, I would love to thank Dr. Carter and Dr. Vemuri for their time, instruction and guidance in my research. Thirdly, I really appreciate all the love and support from my husband, Andrew Gilmore, from my grandparents, my parents and sister-Ms. Ruizhen He, Mr. Ye Chen, Ms. Xiuqun Huang, Mr. Zhuoyu Pan, Ms. Liming Pan, and from my parents-in-law, Mr. and Mrs. Gilmore. Last, I really appreciate all the help and support from my good friends who are willing to give me a hand to help me proceed in my research and life-Abelardo, Weihuang, Tao and Rui.