Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA

Abstract

The modular adder, a critical arithmetic component for residue calculations, is explored in this study through its implementation on a field programmable gate array (FPGA), specifically targeting the Xilinx Zynq-7000 family device. Recent literature reveals an innovative combination of parallel prefix addition and flagged prefix addition techniques for the design of the modular adder. The parallel prefix addition, an evolution of the carry look-ahead addition, utilizes the prefix operation, whereas the flagged prefix addition generates a novel set of intermediate outputs, namely flag bits, to execute the increment operation. This paper extends this innovative combination by demonstrating the FPGA implementation of the existing design via two distinct strategies. The first strategy employs a register-transfer level (RTL) description of the design using the very high-speed integrated circuit hardware description language (VHDL), while the second strategy deploys userdefined intellectual property (IP) blocks for the design implementation. FPGA area and power reports are subsequently generated using VIVADO IDE. The RTL approach illustrates an average savings of 14.30% in slice look-up tables (LUTs) utilization and 1.91% in slice flip-flops (FFs) utilization, suggesting its superiority for applications that prioritize area-efficiency. However, the IP modeling approach emerges as crucial for managing the perpetually increasing complexity of system-on-chip (SoC) designs.