Performance Analysis of Double Gate Hetero Junction Tunnel Fet

doi:10.35940/ijitee.b1058.1292s319

Cited by 7 publications

(1 citation statement)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These two device combinations are designed to achieve excellent performance. Researchers investigated a sum of possible strategies, for instance low band gap substances [3],metal gate work function, Source(S)/Drain(D) material engineering [4] ,strain channel engineering [5], high-k dielectric (or) partially mixture with SiO2 Gate-oxide engineering [6], and multi-gate techniques [7] to enhance the TFETs drive current.…”

Section: Introductionmentioning

confidence: 99%

3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

Dharmireddy¹

2021

TURCOMAT

View full text Add to dashboard Cite

This paper proposed on basis of a perimeter-weighted-sum method for the construction of a 3D-Analytical Modeling of double metalFin structure TFET with dual hetero gate oxide structure. The DM model device dividing into a symmetrical and asymmetrical dual-gate TFETs, and then resolving 3D architectures. The surface potential and the electrical field (E) achieved by resolving the Poisson 3D equation. The drain current (ID) is eventually calculated using Kane tunneling model to calculate the tunneling generation rate. Threshold voltage model also developed based on the charge inversion model. The performance analysis of dual hetero gate oxide Fin TFET device together with dual dielectric engineering techniques results in enhanced drain current and reduced SCE’s of low leakage current, threshold voltage roll-off and drain induced barrier lowering.

show abstract