Performance analysis of FinFET and negative capacitance FET over 6T SRAM

Vaithiyanathan, D.; Muthu, Bharathi Raj; Pushpa, S. Ewins Pon; Seetharaman, R.

doi:10.1109/iccs1.2017.8325989

Cited by 8 publications

(1 citation statement)

References 4 publications

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“…To reduce the power consumption in SRAM array, many attempts for NCFET-based SRAM bit-cell have been done. Previous studies [4], [5] have claimed that the read/write performance of NCFET-based SRAM (vs. conventional SRAM) can be improved. However, there is no discussion on the yield estimation of NCFET-based SRAM.…”

Section: Introductionmentioning

confidence: 99%

NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity

Hong

Choi

Shin

2020

IEEE J. Electron Devices Soc.

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The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) < 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in the 6T SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current (I w), respectively. Then, under process-induced random variation, sensitivities of SNM and I w are extracted. Finally, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated using the cell-sigma.

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Section: Introductionmentioning

confidence: 99%