Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

Abstract

SUMMARYBinary decision diagrams (BDDs) are the most frequently used data structure for the representation and handling of Boolean functions because of their excellent time and space efficiencies. In this article, a reversed BDD-based pass transistor logic (PTL) logic synthesis is presented for low-power and high-performance circuits without exploiting the canonical property of BDDs. The procedure of the reversed BDD transformation into PTL is achieved by a one-to-one correspondence with the BDD node and PTL cell. Layouts are generated for the benchmark circuits and simulated in terms of power dissipation, propagation delay and area. The reversed BDD technique performs better in terms of area, delay and power dissipation due to the regularity, a reduced critical path, less interconnection wires, a multiplexer-based construction of PTL circuits, and less switching activities.

Reversed signal propagation BDD based low‐power pass‐transistor logic synthesis

“…It is observed that the area requirement is same as in Ref. [5] for XOR5 circuit. For most circuits, like CM82a, CM42a, PARKER, MUX, CM138a and Z4ML, because of the additional wires, the area required is more.…”

“…Table VII gives the comparison of the proposed method and the technique reported in Ref. [5] for 65 nm technology and the power supply of 0.7 V in terms of the area and total power dissipation. It is observed that the area requirement is same as in Ref.…”

“…This results in low IR drop, which reduces leakage power and results in low power consumption due to lower output capacitance compared to the forward BDD and Ref. [5].…”

“…Reversed BDD is obtained by reversing the BDD with root nodes at the bottom and terminal nodes at the top. Bhuvaneswari et al [5] carried out a performance analysis of reversed BDD pass‐transistor logic (PTL) realization. It was found that, for most circuits, the area and power consumption were less compared to the forward BDD.…”

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

“…These boolean diagrams can be mapped, one to one in PTL cell. Mapping of boolean representation to PTL logic by reversing their order can achieve efficiency in terms of dynamic power dissipation due to less switching activities [10]. Power dissipation can be reduced in pass transistor technique by replacing NMOS with PMOS [11][12].…”