Performance analysis of thread mappings with a holistic view of the hardware resources

Abstract

With the shift to chip multiprocessors, managing shared resources has become a critical issue in realizing their full potential. Previous research has shown that thread mapping is a powerful tool for resource management. However, the difficulty of simultaneously managing multiple hardware resources and the varying nature of the workloads have impeded the efficiency of thread mapping algorithms. To overcome the difficulties of simultaneously managing multiple resources with thread mapping, the interaction between various microarchitectural resources and thread characteristics must be well understood.This paper presents an in-depth analysis of PARSEC benchmarks running under different thread mappings to investigate the interaction of various thread mappings with microarchitectural resources including, L1 I/D-caches, I/D TLBs, L2 caches, hardware prefetchers, off-chip memory interconnects, branch predictors, memory disambiguation units and the cores. For each resource, the analysis provides guidelines for how to improve its utilization when mapping threads with different characteristics. We also analyze how the relative importance of the resources varies depending on the workloads. Our experiments show that when only memory resources are considered, thread mapping improves an application's performance by as much as 14% over the default Linux scheduler. In contrast, when both memory and processor resources are considered the mapping algorithm achieves performance improvements by as much as 28%. Additionally, we demonstrate that thread mapping should consider L2 caches, prefetchers and off-chip memory interconnects as one resource, and we present a new metric called L2-misses-memory-latency-product (L2MP) for evaluating their aggregated performance impact.

An Efficient Algorithm for Communication-Based Task Mapping

“…Previous studies evaluate the impact of task mapping considering the communication [1], showing that it can influence several hardware resources. In shared memory environments, communication-based task mapping reduces execution time, cache misses and interconnection traffic [2].…”

“…execElInLevel[0] is not used. execElInLevel [1] contains the number of processing units. For positions i, such that 1 < i < nLevels, the value is the number of hardware objects on the respective architecture hierarchy level.…”

“…The different levels of the hierarchy influence the communication performance between the tasks of a parallel application [1]. Communication through a shared cache memory or intra-chip interconnection is faster than communication between processors due to the slower inter-chip interconnections [2].…”

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

“…As parallel applications need to access shared data, the memory hierarchy presents challenges for mapping threads to cores, and data to NUMA nodes [24]. Threads that access a large amount of shared data should be mapped to cores that are close to each other in the memory hierarchy, while data should be mapped to the same NUMA node that the threads that access it are executing on [22].…”

kMAF

“…When scheduling threads, their performance depends on which core each thread is executed, since the memory access performance varies depending on the core and the memory hierarchy [15]. These differences in the memory access latency between cores are due to shared cache levels, different bandwidths and latencies in the interconnections [38]. Regarding memory management, the memory hierarchy introduced non-uniform memory access (NUMA) due to multiple memory controllers in the system.…”