Performance analysis of vedic multiplication technique using FPGA

Chopade, S. S.; Mehta, Rama

doi:10.1109/ibss.2015.7456657

Cited by 5 publications

(6 citation statements)

References 3 publications

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“…The system has reportedly been implemented on the DSCH2 tool and simulated on MICROWIND using 0.25 um technology. In [7], the authors analysed the performance of Vedic multiplication techniques reported to have been implemented using FPGA. Generation of the technology used was not specified, which makes such a study and its proposals a bit unjustified.…”

Section: Literature Surveymentioning

confidence: 99%

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Tomar¹,

George

Tomar

2021

IET Circuits, Devices & Syst

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Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating-point multiplication is an important component. The dynamic range of numbers represented by floating-point arithmetic is very large compared with that of fixed-point numbers of the same bit width. A mantissa similarity investigator (MSI)interfaced multi-precision binary multiplier architecture is developed and can be used in data-intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single-, double-, quadruple-and octuple-precision modes for mantissa multiplication according to the IEEE 754 standard for floating-point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field-programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Literature Surveymentioning

confidence: 99%

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Tomar¹,

George

Tomar

2021

IET Circuits, Devices & Syst

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show abstract

“…Vedic Multiplier is one of the fastest and low power consumption multiplier. It was found to perform better as compared to the other algorithm [3] [4].…”

Section: Introductionmentioning

confidence: 99%

“…Hence Vedic mathematics has high priority in many digital signal processing and image processing application as seen in most of the literature. Chopade and Mehta [3] presented performance analysis of both Nikhiliam and Urdhva Tiryagbhyam algorithm using VHDL language in Xilinx FPGA. It was observed that for 8 bit and 16 bit Urdhva Tiryagbhyam algorithm provides 50% improvement in delay than that of Nikhilam, whereas 100% better than that of binary multiplier.…”

Section: Fig2 Block Diagram Of 4×4 Bit Vedic Multiplier V a Review mentioning

confidence: 99%

“…of the answer is the sum of one number with the deviation of the other. It can be arrived at in any one of the two ways [3]. i) Cross sum of deviation -12 in the second row with the original number 97 in the first row i.e.…”

Section: Nikhilam Navatascaramam Dasatahmentioning

confidence: 99%

“…The techniques in Vedic mathematics are mainly based on sixteen sutras. Among this sixteen sutra's, Urdhva Tiryagbhyam and Nikhilam are used for multiplication [3]. Vedic multipliers provide best results compared to conventional ones and Urdhva Tiryagbhyam sutra architecture is more efficient compared to Nikhilam Sutra.…”

Section: Introductionmentioning

confidence: 99%

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High Speed Vedic Multiplier Based Review With Its Proposed Implementation for Parallel Fir Filter

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Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

Tomar¹,

George

2017

Wireless Pers Commun

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Performance analysis of vedic multiplication technique using FPGA

Cited by 5 publications

References 3 publications

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

High Speed Vedic Multiplier Based Review With Its Proposed Implementation for Parallel Fir Filter

Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

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