Performance analysis of W-CDMA algorithms on a vector DSP

Westermann, Peter; Beier, Gerald; Ait-Harma, Hamza; Schwoerer, Ludwig

doi:10.1109/eccsc.2008.4611698

Cited by 2 publications

(2 citation statements)

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“…However, LIW requires additional register file ports, which increase the area and power demands of the register file. Therefore, implementations of W-CDMA [18] and FFT [19] algorithms on the Embedded Vector Processor (EVP) [17] first have been analyzed in order to decide on the number of LIW slots. An average number of 3.53 parallel instructions per cycle was measured for a radix-2 FFT loop, which contains three FFT stages and vector permutations.…”

Section: Scalable Simd Architecturementioning

confidence: 99%

On the scalability of SIMD processing for software defined radio algorithms

Westermann

Schröder

2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Software defined radio (SDR) systems require programmable architectures that provide high performance combined with high energy efficiency. Wide single instruction, multiple data (SIMD) architectures could potentially satisfy these demands, but only few publications examine the interdependence between the SIMD width and the performance of typical SDR algorithms. In this paper, we present a detailed analysis of three SDR algorithm classes on a newly developed scalable SIMD architecture, which combines SIMD processing with long instruction word (LIW) execution. Although radix-2 and mixed-radix fast Fourier transform, sphere decoding, and low-density parity-check decoding all benefit from SIMD processing, our results show that there are different constraints on the performance.

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Section: Scalable Simd Architecturementioning

confidence: 99%

On the scalability of SIMD processing for software defined radio algorithms

Westermann

Schröder

2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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“…Examples of units that have SIMD processing elements and that are targeted for low-power consuming units, are the NXP Embedded Vector Processor (EVP) [78], [79], the Sandbridge SB3011 [80] and the Icera Livanto [81]. An example university approach is the SODA architecture [67].…”

Section: ) Real-time Reconfigurable Unitsmentioning

confidence: 99%

Software Defined Radio: Challenges and Opportunities

Ulversøy

2010

IEEE Commun. Surv. Tutorials

278

111

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Abstract-Software Defined Radio (SDR) may provide flexible, upgradeable and longer lifetime radio equipment for the military and for civilian wireless communications infrastructure. SDR may also provide more flexible and possibly cheaper multistandard-terminals for end users. It is also important as a convenient base technology for the future context-sensitive, adaptive and learning radio units referred to as cognitive radios. SDR also poses many challenges, however, some of them causing SDR to evolve slower than otherwise anticipated. Transceiver development challenges include size, weight and power issues such as the required computing capacity, but also SW architectural challenges such as waveform application portability. SDR has demanding implications for regulators, security organizations and business developers.Index Terms-Software defined radio, radio communication equipment, software engineering.

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Performance analysis of W-CDMA algorithms on a vector DSP

Cited by 2 publications

References 10 publications

On the scalability of SIMD processing for software defined radio algorithms

On the scalability of SIMD processing for software defined radio algorithms

Software Defined Radio: Challenges and Opportunities

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