Performance and Analysis of Low Power, Areaefficient and High Speed Carryfast Adder

AntoBennet, M.; Sankaranarayanan, S.; BanuPriya, V.; Pretheena, PJaya; Yamini, S.; Supriya, S.

doi:10.21307/ijssis-2017-268

Cited by 1 publication

(2 citation statements)

References 18 publications

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“…The XS-3 coding technique is more advantageous than BCD method as the former involves the nines' complement, which is of extremely important for subtraction purpose. Here both the inputs and outputs are totally four bits; the logic expressions of the conversion formulas employ NAND-gates, NOT-gate, XOR-gate and XNOR-gate [3,23,24].…”

Section: Bcd To Excess-3 Converter Circuit Based On Proposed Logicmentioning

confidence: 99%

“…Previous works on adiabatic BCD to Excess-3 code converters included efficient charge recovery logic (ECRL), positive feedback adiabatic logic (PFAL), quantum dot cellular automata (QCA), and adiabatic logic array (ALA) [21][22][23][24]. However, this work analysed the entire power consumption of the circuit; the BCD to Excess-3 code converter relied on the ordinary standard-adiabatic logic method and came up with a novel circuit design (proposed technique) that consumes considerably less power.…”

Section: Introductionmentioning

confidence: 99%

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A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Vanlalchaka

Maity

2023

Eng. Res. Express

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Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3µm CMOS technology, with channel length and width set at 0.3µm and 0.75µm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively

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Section: Bcd To Excess-3 Converter Circuit Based On Proposed Logicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Vanlalchaka

Maity

2023

Eng. Res. Express

View full text Add to dashboard Cite

show abstract

Performance and Analysis of Low Power, Areaefficient and High Speed Carryfast Adder

Cited by 1 publication

References 18 publications

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

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