Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters

Mantovani, Filippo; Calore, Enrico

doi:10.3390/jlpea8020013

Cited by 26 publications

(12 citation statements)

References 42 publications

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“…We plan to extend this work also to the second release of the ThunderX chip which is expected to be widely adopted in the HPC market [8] and moreover we expect to be able to access also non-standard power related registers embedded in this SoC [7], as done for other architectures [36]. The possibility to read power figures using PAPI [37], would enable also fine grained energy analyses [29], [38] without the need for external power-meters [39].…”

Section: Discussionmentioning

confidence: 99%

Advanced Performance Analysis of HPC Workloads on Cavium ThunderX

Calore

Mantovani

Ruíz

2018

2018 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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The interest towards Arm based platforms as HPC solutions increased significantly during the last 5 years. In this paper we show that, in contrast to the early days of pioneer tests, several application performance analysis techniques can now be applied also to Arm based SoCs. To show the possibilities offered by the available tools, we provide as an example, the analysis of a Lattice Boltzmann HPC production code, highly optimized for several architectures and now ported also to Armv8. We tested it on a system based on a production silicon, Cavium CN8890 SoC. In particular, as performance analysis tools we adopt Extrae and Paraver, making use of the PAPI support, initially developed by us for the ThunderX platform, and now available also upstream. The contribution of this paper is twofold: first, we demonstrate that performance analysis tools available on standard HPC platforms, independently from the CPU providers, are nowadays available also for Arm SoCs; second, we actually optimize an HPC application for this platforms, showing similarities with other architectures.

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Section: Discussionmentioning

confidence: 99%

Advanced Performance Analysis of HPC Workloads on Cavium ThunderX

Calore

Mantovani

Ruíz

2018

2018 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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“…Popular tools to read the PMCs on a given platform include Likwid [47], Linux Perf [48], PAPI [43] and Intel PCM [42]. Extrae and Paraver tools [49,50] can also be used to gather the PMCs. These tools are built on top of PAPI.…”

Section: Comparison Of Dynamic Energy Consumption Using Pmc-based Enementioning

confidence: 99%

A Comparative Study of Methods for Measurement of Energy of Computing

et al. 2019

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Energy of computing is a serious environmental concern and mitigating it is an important technological challenge. Accurate measurement of energy consumption during an application execution is key to application-level energy minimization techniques. There are three popular approaches to providing it: (a) System-level physical measurements using external power meters; (b) Measurements using on-chip power sensors and (c) Energy predictive models. In this work, we present a comprehensive study comparing the accuracy of state-of-the-art on-chip power sensors and energy predictive models against system-level physical measurements using external power meters, which we consider to be the ground truth. We show that the average error of the dynamic energy profiles obtained using on-chip power sensors can be as high as 73% and the maximum reaches 300% for two scientific applications, matrix-matrix multiplication and 2D fast Fourier transform for a wide range of problem sizes. The applications are executed on three modern Intel multicore CPUs, two Nvidia GPUs and an Intel Xeon Phi accelerator. The average error of the energy predictive models employing performance monitoring counters (PMCs) as predictor variables can be as high as 32% and the maximum reaches 100% for a diverse set of seventeen benchmarks executed on two Intel multicore CPUs (one Haswell and the other Skylake). We also demonstrate that using inaccurate energy measurements provided by on-chip sensors for dynamic energy optimization can result in significant energy losses up to 84%. We show that, owing to the nature of the deviations of the energy measurements provided by on-chip sensors from the ground truth, calibration can not improve the accuracy of the on-chip sensors to an extent that can allow them to be used in optimization of applications for dynamic energy. Finally, we present the lessons learned, our recommendations for the use of on-chip sensors and energy predictive models and future directions.

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“…Finally, for the work on Dibona, our Arm-based platform, we acknowledge the previous work of the Mont-Blanc project [6] as well es the evaluation of more recent Arm-based architectures [19], [20].…”

Section: Related and Future Workmentioning

confidence: 99%

TensorFlow on State-of-the-Art HPC Clusters: A Machine Learning use Case

Ramirez-Gargallo

García-Gasulla

Mantovani

2019

2019 19th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGRID)

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The recent rapid growth of the data-flow programming paradigm enabled the development of specific architectures, e.g., for machine learning. The most known example is the Tensor Processing Unit (TPU) by Google. Standard data-centers, however, still can not foresee large partitions dedicated to machine learning specific architectures. Within data-centers, the High-Performance Computing (HPC) clusters are highly parallel machines targeting a broad class of compute-intensive workflows, as such they can be used for tackling machine learning challenges. On top of this, HPC architectures are rapidly changing, including accelerators and instruction sets other than the classical x86 CPUs. In this blurry scenario, identifying which are the best hardware/software configurations to efficiently support machine learning workloads on HPC clusters is not trivial. In this paper, we considered the workflow of TensorFlow for image recognition. We highlight the strong dependency of the performance in the training phase on the availability of arithmetic libraries optimized for the underlying architecture. Following the example of Intel leveraging the MKL libraries for improving the TensorFlow performance, we plugged the Arm Performance Libraries into TensorFlow and tested on an HPC cluster based on Marvell ThunderX2 CPUs. Also, we performed a scalability study on three state-of-the-art HPC clusters based on different CPU architectures, x86 Intel Skylake, Arm-v8 Marvell ThunderX2, and PowerPC IBM Power9.

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Performance and Power Analysis of HPC Workloads on Heterogeneous Multi-Node Clusters

Cited by 26 publications

References 42 publications

Advanced Performance Analysis of HPC Workloads on Cavium ThunderX

Advanced Performance Analysis of HPC Workloads on Cavium ThunderX

A Comparative Study of Methods for Measurement of Energy of Computing

TensorFlow on State-of-the-Art HPC Clusters: A Machine Learning use Case

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