Performance and Power Consumption Analysis of DVFS-Enabled H.264 Decoder on Heterogeneous Multi-Core Platform

Abstract

Power consumption becomes a very important criterion for the portable embedded devices and, therefore, many Dynamic Voltage/Frequency Scaling (DVFS) techniques have been introduced. This paper is trying to break down and analyze the power consumed by three main components, DSP logic, local memory, and the external DDR2, of a multi-core SoC platform. There are four configurations for this SoC platform: one DSP with full and half clock rates and two DSP's with full and half clock rates. The DSP's in the SoC are clone in the hardware architecture and execute the same H.264/AVC decoder software in all scenarios. With this breakdown, we can figure out the key factors for energy saving and further offer some valuable suggestions for the power management and embedded multi-core SoC designs.

Power Modeling for Video Streaming Applications on Mobile Devices

“…With a special software application, the two high-performance processor cores are disabled and the two low-power processor cores are set to high-performance processing because initial tests showed that at least two processors need to be enabled for fluid playback. This setting is chosen to reduce the effect of dynamic voltage and frequency scaling (DVFS, [40]). Furthermore, the performance governor of the GPU is also set to 'performance'.…”

Estimating the HEVC decoding energy using the decoder processing time

“…At the same time it has to be ensured that no other process, like idle power or background system processes, disturb the measurements. Such setups have, e.g., been proposed in [2], [3], [4], or [5].…”