Performance and Power Solutions for Caches Using 8T SRAM Cells

Farahani, Mostafa; Baniasadi, Amirali

doi:10.1109/microw.2012.17

Cited by 3 publications

(5 citation statements)

References 15 publications

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“…This paper is an extension of our earlier paper [12]. The following are the differences between this paper and the earlier workshop publication.…”

Section: Background and Related Workmentioning

confidence: 86%

“…The second improvement in the RMW can be achieved by detecting the silent writes [16] and avoiding the associated writeback operations [12]. The silent write refers to a write request that writes the value that is already stored, hence not making any difference [16].…”

Section: Motivationmentioning

confidence: 99%

“…In this paper, we identify and present the inefficiency of the RMW. We show that a considerable share of the cache traffic overhead imposed by the RMW (including both the read and the write operations) is either redundant or unnecessary and consequently can be eliminated without compromising the coherency and the correctness concerns [12]. We propose two solutions, Write Grouping (WG) and WG and Read Bypassing (WG + RB) to reduce the overhead associated with the RMW.…”

Section: Introductionmentioning

confidence: 99%

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Column selection solutions for L 1 data caches implemented using eight‐transistor cells

Farahani

Baniasadi

2014

IET Computers & Digital Techniques

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Voltage scaling can reduce power dissipation significantly. SRAM cells (which are traditionally implemented by using six-transistor cells) can limit voltage scaling because of stability concerns. Eight-transistor (8T) cells were proposed to enhance cell stability under voltage scaling. 8T cells, however, suffer from costly write operations caused by the column selection issue. A proposed technique, Read-Modify-Write (RMW), addresses this issue at the expense of extra read operations. The extra cache access affects performance and power dissipation negatively. In this study, the authors show that a large share of the cache accesses in RMW is unnecessary. To address this inefficiency, they propose two micro-architectural solutions with the aim of reducing the overhead imposed by RMW. The authors first proposed technique, Write Grouping (WG), relies on a buffering mechanism that identifies the redundant and the unnecessary cache accesses imposed by RMW and eliminates them. Their second technique, WG and Read Bypassing (WG + RB), improves the WG's efficiency further at a negligible area cost. Their simulation results show that on average, WG and WG + RB reduce RMW's cache traffic overhead by 15% and 20%, respectively. They show that WG and WG + RB also improve average performance by 30% and 37%, respectively.

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“…This paper is an extension of our earlier paper [12]. The following are the differences between this paper and the earlier workshop publication.…”

Section: Background and Related Workmentioning

confidence: 86%

Section: Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Column selection solutions for L 1 data caches implemented using eight‐transistor cells

Farahani

Baniasadi

2014

IET Computers & Digital Techniques

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“…The need for a compulsory read before write contributes additionally to power dissipation. We propose a new technique called Writeback grouping (WBG) that is a modified version of the writegrouping proposal presented in [17] to address these concerns. The address of the last-accessed (write) cache set and its associated tags are stored in a small buffer inside the cache controller called the Tag-buffer.…”

Section: Table II Xor Logic During Read For Inverting Input/output Bamentioning

confidence: 99%

“…The leakage power on-average is 4X lesser compared to a regular 6T-SRAM [18]. The total area required by the Tag-Buffer is approximately 150 bits considering a 48-bit virtual address [17]. The largest area-overhead is incurred due to the counter that maintains the number of read requests received.…”

Section: ) V Th Degradationmentioning

confidence: 99%

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches

Ganapathy

Canal

González

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Abstract-Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical variations of process parameters, it can potentially render systems dysfunctional in certain scenarios. Data caches suffer the most from such phenomenon because of the unbalanced duty cycle ratio of SRAM cells and maximum intrinsic susceptibility to process variations. In this paper, we propose a novel NBTI-aware technique, invertRead-Modify-Write (iRMW) that can improve the functional yield of the data cache significantly over its lifetime. Using architecture-level benchmarks, we first analyse the impact of activity factor and workload variation on NBTI-induced failures in data caches. iRMW is then used as a means to balance the duty cycle by alternating between recovery and stress cycle upon successive read accesses to the cache line. The highly transient nature of the data stored in L1 data cache aides this process of recovery upon using iRMW. A unique feature of iRMW is its intelligent use of low-leakage & NBTI-tolerant embedded-DRAM cells as an alternative to SRAM-cells for storing important state information. Our experiments conducted using SPEC2006 and PhysicsBench workloads show that on-average the cache failure probability can be reduced by 22%, 33% and 36% after two, four and eight years of processor usage respectively. In addition to being extremely power-frugal, use of eDRAM reduces total area footprint of iRMW tremendously.

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