Performance and transport analysis of vertically stacked p-FET SOI nanowires

Abstract

This work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution.

New method for individual electrical characterization of stacked SOI nanowire MOSFETs

“…Aiming to step up into the solution of these problems, vertically stacked p-NWs combining both inner spacers and SiGe S/D have been recently fabricated [3]. Overall performance and transport of these stacked NWs have been investigated in [5], but still no individual electrical characterization of each NW level is available, which could be valuable for technology optimization. A methodology to separate the channels conduction was firstly proposed and applied to Multi-Gate devices using the effect of the applied back bias VB [6].…”