Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node

Shin, Changhwan; Damrongplasit, Nattapol; Sun, Xun; Tsukamoto, Yasumasa; Nikolić, Borivoje; Liu, Tsu‐Jae King

doi:10.1109/ted.2011.2139213

Cited by 25 publications

(11 citation statements)

References 38 publications

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“…However, if the capacity of the SRAM array is increased significantly, the amount of data for the SRAM margin metrics must be increased to estimate the metric to the six-sigma level [32]. However, as mentioned before, the failure events in a single SRAM cell are rare events.…”

Section: Standard Monte Carlo Simulationmentioning

confidence: 99%

Applications in Static Random Access Memory (SRAM)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip. Today, it is feasible to fabricate a single SRAM cell in a 0.04999-µm 2 area [1]. However, as the transistors are aggressively scaled down, the impacts of the process-induced random variations on the device performance are dramatically increased [2]. The term "process-induced random variations" indicates that the process/fabrication steps such as doping, lithography, etching, chemical mechanical polishing (CMP), and so on, induce these random variations [3]. The well-known random variation sources caused by the aforementioned process steps are random dopant fluctuations (RDF) [4] [also known as random dopant distributions (RDD)] [5], line edge roughness (LER) [6], work function variations (WFV) [7] (also known as metal grain granularity (MGG) [8]), and oxide thickness variations [9]. Aforementioned random variations cause variations in parameters such as effective channel length and threshold voltage of each transistor. Then, the mismatches in the effective channel lengths and threshold voltages between two neighboring transistors cause degradations in the stability of the SRAM cells, which consist of a few transistors (e.g., 6 transistors for 6T SRAM cell) [10]. This is because each transistor of a single SRAM cell should be balanced in order to make it stable for the read/write/retention operations [11]. Further detailed information about how to balance the different transistors of a single SRAM cell, and how badly the stabilities of the SRAM cells are degraded by process-induced variations, will be provided later.Since random variations significantly affect the performance of SRAM cells, it is irrefutable that random variations are one of the key factors in the SRAM cell design. Furthermore, it is important to look for "random variation"-tolerant SRAM designs because random variations cannot be controlled, as systematic variations are controlled [12]. In order to find the random-variation-tolerant SRAM cell designs, understanding how the SRAM cell operates and how the process-induced

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Section: Standard Monte Carlo Simulationmentioning

confidence: 99%

Applications in Static Random Access Memory (SRAM)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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“…The LER-induced V TH variation in CMOS devices is mostly dominated by a few short channels (called lucky channels) along the channel width direction, and therefore, the short-channel-effect robust device structures can reduce the LER-induced V TH variation in the given LER profile. For example, multigate devices such as FinFETs and tri-gate MOSFETs [11,12] and ultra-thin-body devices such as FD-SOI MOSFETs [13] are good candidates to overcome the V TH variation by the LER, primarily, because of their improved gate-to-channel capacitive coupling (in comparison with conventional planar bulk MOSFETs).…”

Section: Understanding: Random Variations 1 Line Edge Roughness mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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“…To surmount the LER-induced V TH variation, a device structure that is strongly immune to short-channel effects should be used. For example, multi-gate devices such as FinFETs and tri-gate MOSFETs [6,7] and ultra-thin-body devices such as Fully Depleted Silicon-On-Insulator (FD-SOI) MOSFETs [8] are good candidates to overcome the LER-induced V TH variation, due primarily to their improved gate-to-channel capacitive coupling (in comparison with conventional planar bulk MOSFETs).…”

Section: Introductionmentioning

confidence: 99%

State-of-the-art silicon device miniaturization technology and its challenges

Shin

2014

IEICE Electron. Express

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Complementary Metal-Oxide-Semiconductor (CMOS) process and silicon device technologies have progressed dramatically in the last 950 years. The achievements of semiconductor industry have dramatically improved the human lifestyle making it smarter. One of the biggest factors in this change is the continued CMOS scaling. However, at sub-30-nm CMOS technology nodes, one of the main technical barriers for reducing the size of CMOS silicon devices is the parametric failure caused by random variations such as line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). This paper discusses these issues in terms of (1) the physical understanding and quantitative evaluation of each random variation source, and (2) the technical solutions to address each of these random variation issues. Lastly, the silicon device scaling scenario from the past, the present and through to the future (i.e., 90 nm technology down to sub-10-nm technology) is briefly discussed.

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Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node

Cited by 25 publications

References 38 publications

Applications in Static Random Access Memory (SRAM)

Applications in Static Random Access Memory (SRAM)

Analysis of Random Variations and Variation-Robust Advanced Device Structures

State-of-the-art silicon device miniaturization technology and its challenges

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