Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip

Abstract

SUMMARYNetwork on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.

Energy- and Traffic-Balance-Aware Mapping Algorithm for Network-on-Chip

“…In order to show the performance of algorithm in application specific benchmark, the Video Objective Plane Decoder (VOPD) with 16 cores is introduced in simulation [8], [9]. Simultaneously, the mapping algorithms based on the Nondominated Sorting Genetic Algorithm II (NSGA-II) [10] and random mapping algorithm are compared respectively.…”

BMM: A Binary Metaheuristic Mapping Algorithm for Mesh-Based Network-on-Chip

“…For a given application, an application can be viewed as an Application Core Graph (ACG). Similarly, the target NoC topology can be represented by a Topology Architecture Graph (TAG) [2]. Mathematically, the detailed definitions are shown as follows:…”

“…Since the chromosome of Genetic Algorithm (GA) is integer string encoding, GA becomes one of the most popular population-based MAs for NoC mapping. Sun et al [2] integrate the advantages of GA and Simulated Annealing (SA) Algorithm to reduce the energy consumption of NoC. A GA-based approach is introduced to carry out the map- ping of application on NoC in [3].…”