Performance Benefits of Monolithically Stacked 3-D FPGA

Abstract

Abstract-The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are ≤ 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal-oxide-semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node.

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

“…If 3D integration technology is introduced in the future to stack several mrFPGAs together, at least two more times of improvements in density and speedup, i.e. 10x and 4.5x respectively, are both expected, according to the experimental results on 3D architecture in [17].…”

“…A 3D FPGA architecture was proposed in [17]. It partitions the transistors in the routing structure and logic structure of conventional FPGA into multiple active layers and stacks the layers via monolithic stacking, a 3D integration technology the author proposes to use as shown in Fig.…”

“…In [14] and [18] two FPGA architectures are proposed using emerging NVMs and through-silicon-via (TSV) based 3D integration. Similar to the monolithic stacking in [17], they also move all the transistors in the routing structure of FPGA to the top die over the logic structure die with TSV connections between them as shown in Fig. 2b.…”

Three DIMENSIONAL-CHIPS

“…This approach requires monolithic 3D integration because of the high density of inter-layer via required. The study in [6] has shown that such stacking cans achieve3.2 times higher logic density, 1.7 times lower delay, and 1.7 times lower dynamic power consumption than a baseline2D-FPGA implemented in 65nm CMOS technology. These improvements are achieved with appropriate optimization of buffer and transistor sizes, but without any change to the FPGA architecture.…”

FPGA Architecture: Survey and Challenges

“…Renewed interest in 3D device packaging has direct applicability to FPGA logic [140] and routing structures [139]. As transistor channel widths shrink deep into the submicron realm, the manufacturability of reliable FPGA routing becomes an issue.…”