Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center

Lösch, Achim; Beisel, Tobias; Kenter, Tobias; Plessl, Christian; Platzner, Marco

doi:10.3850/9783981537079_0987

Cited by 10 publications

(5 citation statements)

References 16 publications

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“…Power Clustering: We note that the up-to-date power management techniques [36], [37] do not require the precise power values for decision making, and therefore, some errors induced in the power monitoring schemes are allowed. Based on this observation, we implement a power clustering stage following the attribute selection in order to trim down the complexity of power representation.…”

Section: Model Generation Flowmentioning

confidence: 99%

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System

Lin

Sinha

Zhang

2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Decision trees are machine learning models commonly used in various application scenarios. In the era of big data, traditional decision tree induction algorithms are not suitable for learning large-scale datasets due to their stringent data storage requirement. Online decision tree learning algorithms have been devised to tackle this problem by concurrently training with incoming samples and providing inference results. However, even the most up-to-date online tree learning algorithms still suffer from either high memory usage or high computational intensity with dependency and long latency, making them challenging to implement in hardware. To overcome these difficulties, we introduce a new quantile-based algorithm to improve the induction of the Hoeffding tree, one of the state-of-the-art online learning models. The proposed algorithm is lightweight in terms of both memory and computational demand, while still maintaining high generalization ability. A series of optimization techniques dedicated to the proposed algorithm have been investigated from the hardware perspective, including coarse-grained and finegrained parallelism, dynamic and memory-based resource sharing, pipelining with data forwarding. Following this, we present Hard-ODT, a high-performance, hardware-efficient and scalable online decision tree learning system on a field-programmable gate array (FPGA) with system-level optimization techniques. Performance and resource utilization are modeled for the complete learning system for early and fast analysis of the tradeoff between various design metrics. Finally, we propose a design flow in which the proposed learning system is applied to FPGA run-time power monitoring as a case study. Experimental results show that our proposed algorithm outperforms the state-of-theart Hoeffding tree learning method, leading to 0.05% to 12.3% improvement in inference accuracy. Real implementation of the complete learning system on the FPGA demonstrates a 384× to 1581× speedup in execution time over the state-of-the-art design. The power modeling strategy with Hard-ODT achieves an average power prediction error within 4.93% of a commercial gate-level power estimation tool.

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Section: Model Generation Flowmentioning

confidence: 99%

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System

Lin

Sinha

Zhang

2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Consequently, the execution through HTrOP (dominated by motion with 17.6 seconds) leads to a 5.6× improvement in end-to-end execution time, even though motion was migrated during the execution from the PHI to the GPGPU. A study of different scenarios and measurements of the affinity of kernels for various accelerators is presented by Lösch et al [39].…”

Section: Concurrent Execution With Multiple Applications and Hotspotsmentioning

confidence: 99%

Transparent Acceleration for Heterogeneous Platforms With Compilation to OpenCL

Riebler

Vaz

Kenter

et al. 2019

ACM Trans. Archit. Code Optim.

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Multi-accelerator platforms combine CPUs and different accelerator architectures within a single compute node. Such systems are capable of processing parallel workloads very efficiently while being more energy efficient than regular systems consisting of CPUs only. However, the architectures of such systems are diverse, forcing developers to port applications to each accelerator using different programming languages, models, tools, and compilers. Developers not only require domain-specific knowledge but also need to understand the low-level accelerator details, leading to an increase in the design effort and costs.To tackle this challenge, we propose a compilation approach and a practical realization called HTrOP that is completely transparent to the user. HTrOP is able to automatically analyze a sequential CPU application, detect computational hotspots, and generate parallel OpenCL host and kernel code. The potential of HTrOP is demonstrated by offloading hotspots to different OpenCL-enabled resources (currently the CPU, the generalpurpose GPU, and the manycore Intel Xeon Phi) for a broad set of benchmark applications. We present an in-depth evaluation of our approach in terms of performance gains and energy savings, taking into account all static and dynamic overheads. We are able to achieve speedups and energy savings of up to two orders of magnitude, if an application has sufficient computational intensity, when compared to a natively compiled application.This article is an extension of a conference paper/poster at PPoPP'18 [49]. Prior work only outlined the tool flow and the parallelization mechanism. Evaluation is entirely new, including energy measurements and trends over several data points per application.

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“…In order to generalize the dynamic power models at high level, a set of key signals are captured and we monitor their switching activities formulated in Equation (2), where a(•) is the activity function which returns the difference of signal transition counts s(•) on the signal set sig over the estimation period from t start to t end . For a large design containing millions of nets, it is vital to identify a subset of discriminative and informative nets that are strongly indicative of the power.…”

Section: A Activity Trace Flow (Atf)mentioning

confidence: 99%

“…These tools are fully aware of the internal hardware implementation and they can provide accurate power estimation during design time, thus helping designers to tune their circuits using power optimization techniques during development periods. Nevertheless, there is a burgeoning interest in applying runtime power management techniques, e.g., dynamic voltage frequency scaling (DVFS) [1] and task scheduling techniques [2]. Such runtime strategies make it a necessity to be aware of the runtime dynamic power consumption for the applications running on FPGA.…”

Section: Introductionmentioning

confidence: 99%

Decision tree based hardware power monitoring for run time dynamic power management in FPGA

Lin

Zhang

Sinha

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Fine-grained runtime power management techniques could be promising solutions for power reduction. Therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or hundreds of clock cycles). In this paper, we leverage a decision-tree-based power modeling approach to establish finegrained hardware power monitoring on FPGA platforms. A generic and complete design flow is developed to implement the decision tree power model which is capable of precisely estimating dynamic power in a fine-grained manner. A flexible architecture of the hardware power monitoring is proposed, which can be instrumented in any RTL design for runtime power estimation, dispensing with the need for extra power measurement devices. Experimental results of applying the proposed model to benchmarks with different resource types reveal an average error up to 4% for dynamic power estimation. Moreover, the overheads of area, power and performance incurred by the power monitoring circuitry are extremely low. Finally, we apply our power monitoring technique to the power management using phase shedding with an on-chip multi-phase regulator as a proof of concept and the results demonstrate 14% efficiency enhancement for the power supply of the FPGA internal logic.

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Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center

Cited by 10 publications

References 16 publications

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System

Transparent Acceleration for Heterogeneous Platforms With Compilation to OpenCL

Decision tree based hardware power monitoring for run time dynamic power management in FPGA

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