2013 IEEE 31st International Conference on Computer Design (ICCD) 2013
DOI: 10.1109/iccd.2013.6657097
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Performance-controllable shared cache architecture for multi-core soft real-time systems

Abstract: Multi-core processors with shared L2 caches can improve performance and integrate several functions of real-time systems on a single chip. However, tasks running on different cores increase interferences in the shared L2 cache, resulting in more deadline misses and, consequently, worse quality of real-time tasks. This is mainly because of the blind sharing of the L2 cache by multiple tasks running on different cores. We propose a novel performance-controllable shared L2 cache architecture that can alleviate th… Show more

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