Performance-driven placement procedure for low power

Abstract

SUMMARYDeep-Sub-Micron (DSM) technologies of 0.18 µm and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, it is important to consider reducing power consumption, improving interconnection delay, and dispersing wire congestion at the initial phase of layout design. In this paper, we proposed a novel performance-driven placement algorithm. The proposed algorithm based on Genetic Algorithm (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for reducing power consumption, improving interconnection delay, and dispersing wire congestion. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA with consideration of power, delay, and congestion. Results show improvement of 11.7% for the total wire length of the nets with high SW rate, 22.5% for the worst path delay, and 15.9% for wire congestion on average.