2015
DOI: 10.1145/2770872
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Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs

Abstract: The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely hi… Show more

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Cited by 5 publications
(11 citation statements)
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“…Moreover, to alleviate the second-order lithographic errors and the proximity effects, the capacitor array should be surrounded by the dummy unit capacitors [4,16]. This implies that, with this routing method and layout implementation, we can focus only on placement of unit capacitors [15,22]. …”
Section: B Parasitic Capacitances and Layoutmentioning
confidence: 99%
See 4 more Smart Citations
“…Moreover, to alleviate the second-order lithographic errors and the proximity effects, the capacitor array should be surrounded by the dummy unit capacitors [4,16]. This implies that, with this routing method and layout implementation, we can focus only on placement of unit capacitors [15,22]. …”
Section: B Parasitic Capacitances and Layoutmentioning
confidence: 99%
“…In fact, the success of resulting in better ratio mismatch was attributed to place both C0 and C1 at the central entries of the array [22]. Moreover, the placement with large overall correlation coefficient L cannot result in better performance [22].…”
Section: Performance Metrics Of Uc Placementmentioning
confidence: 99%
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